PGXP: Treat add rd, rs, zero as moves
Fixes exploding vertices in BIOS intro. Needs further investigation as to why this fixes it - clearly the actual oepration is incorrect.
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59ac365b52
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@ -901,17 +901,20 @@ void CPU_ADDI(u32 instr, u32 rtVal, u32 rsVal)
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tempImm.d = imm(instr);
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tempImm.sd = (tempImm.sd << 16) >> 16; // sign extend
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ret.x = (float)f16Unsign(ret.x);
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ret.x += (float)tempImm.w.l;
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if (tempImm.d != 0)
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{
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ret.x = (float)f16Unsign(ret.x);
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ret.x += (float)tempImm.w.l;
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// carry on over/underflow
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float of = (ret.x > USHRT_MAX) ? 1.f : (ret.x < 0) ? -1.f : 0.f;
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ret.x = (float)f16Sign(ret.x);
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// ret.x -= of * (USHRT_MAX + 1);
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ret.y += tempImm.sw.h + of;
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// carry on over/underflow
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float of = (ret.x > USHRT_MAX) ? 1.f : (ret.x < 0) ? -1.f : 0.f;
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ret.x = (float)f16Sign(ret.x);
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// ret.x -= of * (USHRT_MAX + 1);
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ret.y += tempImm.sw.h + of;
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// truncate on overflow/underflow
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ret.y += (ret.y > SHRT_MAX) ? -(USHRT_MAX + 1) : (ret.y < SHRT_MIN) ? USHRT_MAX + 1 : 0.f;
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// truncate on overflow/underflow
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ret.y += (ret.y > SHRT_MAX) ? -(USHRT_MAX + 1) : (ret.y < SHRT_MIN) ? USHRT_MAX + 1 : 0.f;
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}
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CPU_reg[rt(instr)] = ret;
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CPU_reg[rt(instr)].value = rtVal;
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@ -1069,33 +1072,40 @@ void CPU_ADD(u32 instr, u32 rdVal, u32 rsVal, u32 rtVal)
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Validate(&CPU_reg[rs(instr)], rsVal);
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Validate(&CPU_reg[rt(instr)], rtVal);
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// iCB: Only require one valid input
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if (((CPU_reg[rt(instr)].flags & VALID_01) != VALID_01) != ((CPU_reg[rs(instr)].flags & VALID_01) != VALID_01))
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if (rtVal != 0)
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{
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MakeValid(&CPU_reg[rs(instr)], rsVal);
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MakeValid(&CPU_reg[rt(instr)], rtVal);
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// iCB: Only require one valid input
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if (((CPU_reg[rt(instr)].flags & VALID_01) != VALID_01) != ((CPU_reg[rs(instr)].flags & VALID_01) != VALID_01))
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{
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MakeValid(&CPU_reg[rs(instr)], rsVal);
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MakeValid(&CPU_reg[rt(instr)], rtVal);
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}
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ret = CPU_reg[rs(instr)];
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ret.x = (float)f16Unsign(ret.x);
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ret.x += (float)f16Unsign(CPU_reg[rt(instr)].x);
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// carry on over/underflow
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float of = (ret.x > USHRT_MAX) ? 1.f : (ret.x < 0) ? -1.f : 0.f;
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ret.x = (float)f16Sign(ret.x);
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// ret.x -= of * (USHRT_MAX + 1);
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ret.y += CPU_reg[rt(instr)].y + of;
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// truncate on overflow/underflow
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ret.y += (ret.y > SHRT_MAX) ? -(USHRT_MAX + 1) : (ret.y < SHRT_MIN) ? USHRT_MAX + 1 : 0.f;
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// TODO: decide which "z/w" component to use
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ret.halfFlags[0] &= CPU_reg[rt(instr)].halfFlags[0];
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ret.gFlags |= CPU_reg[rt(instr)].gFlags;
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ret.lFlags |= CPU_reg[rt(instr)].lFlags;
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ret.hFlags |= CPU_reg[rt(instr)].hFlags;
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}
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else
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{
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ret = CPU_reg[rs(instr)];
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}
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ret = CPU_reg[rs(instr)];
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ret.x = (float)f16Unsign(ret.x);
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ret.x += (float)f16Unsign(CPU_reg[rt(instr)].x);
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// carry on over/underflow
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float of = (ret.x > USHRT_MAX) ? 1.f : (ret.x < 0) ? -1.f : 0.f;
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ret.x = (float)f16Sign(ret.x);
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// ret.x -= of * (USHRT_MAX + 1);
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ret.y += CPU_reg[rt(instr)].y + of;
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// truncate on overflow/underflow
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ret.y += (ret.y > SHRT_MAX) ? -(USHRT_MAX + 1) : (ret.y < SHRT_MIN) ? USHRT_MAX + 1 : 0.f;
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// TODO: decide which "z/w" component to use
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ret.halfFlags[0] &= CPU_reg[rt(instr)].halfFlags[0];
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ret.gFlags |= CPU_reg[rt(instr)].gFlags;
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ret.lFlags |= CPU_reg[rt(instr)].lFlags;
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ret.hFlags |= CPU_reg[rt(instr)].hFlags;
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ret.value = rdVal;
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