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CPU: Fix AdEL/IBE on instruction fetch 

CAUSE and EPC were swapped for the latter.
This commit is contained in:
Stenzek 2024-12-27 13:28:42 +10:00
parent 4b34825afd
commit 4e5b4ba071
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1 changed files with 13 additions and 4 deletions
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17
src/core/cpu_core.cpp
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@ -2706,10 +2706,13 @@ ALWAYS_INLINE_RELEASE bool CPU::DoInstructionRead(PhysicalMemoryAddress address,
return true; return true;
} }
else else [[unlikely]]
{ {
if (raise_exceptions) if (raise_exceptions)
CPU::RaiseException(address, Cop0Registers::CAUSE::MakeValueForException(Exception::IBE, false, false, 0)); {
g_state.cop0_regs.BadVaddr = address;
RaiseException(Cop0Registers::CAUSE::MakeValueForException(Exception::IBE, false, false, 0), address);
}
std::memset(data, 0, sizeof(u32) * word_count); std::memset(data, 0, sizeof(u32) * word_count);
return false; return false;
@ -2871,7 +2874,13 @@ ALWAYS_INLINE_RELEASE bool CPU::FetchInstruction()
bool CPU::FetchInstructionForInterpreterFallback() bool CPU::FetchInstructionForInterpreterFallback()
{ {
DebugAssert(Common::IsAlignedPow2(g_state.npc, 4)); if (!Common::IsAlignedPow2(g_state.npc, 4)) [[unlikely]]
{
// The BadVaddr and EPC must be set to the fetching address, not the instruction about to execute.
g_state.cop0_regs.BadVaddr = g_state.npc;
RaiseException(Cop0Registers::CAUSE::MakeValueForException(Exception::AdEL, false, false, 0), g_state.npc);
return false;
}
const PhysicalMemoryAddress address = g_state.npc; const PhysicalMemoryAddress address = g_state.npc;
switch (address >> 29) switch (address >> 29)
@ -2881,7 +2890,7 @@ bool CPU::FetchInstructionForInterpreterFallback()
case 0x05: // KSEG1 - physical memory uncached case 0x05: // KSEG1 - physical memory uncached
{ {
// We don't use the icache when doing interpreter fallbacks, because it's probably stale. // We don't use the icache when doing interpreter fallbacks, because it's probably stale.
if (!DoInstructionRead<false, false, 1, true>(address, &g_state.next_instruction.bits)) if (!DoInstructionRead<false, false, 1, true>(address, &g_state.next_instruction.bits)) [[unlikely]]
return false; return false;
} }
break; break;