CPU: Add missing cop0 register reads
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9f36384752
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459db392e7
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@ -15,14 +15,26 @@ Core::~Core() = default;
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bool Core::Initialize(Bus* bus)
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{
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m_bus = bus;
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// From nocash spec.
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m_cop0_regs.PRID = UINT32_C(0x00000002);
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return true;
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}
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void Core::Reset()
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{
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m_regs = {};
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m_regs.npc = RESET_VECTOR;
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FetchInstruction();
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m_cop0_regs.BPC = 0;
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m_cop0_regs.BDA = 0;
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m_cop0_regs.JUMPDEST = 0;
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m_cop0_regs.BadVaddr = 0;
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m_cop0_regs.BDAM = 0;
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m_cop0_regs.BPCM = 0;
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m_cop0_regs.EPC = 0;
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SetPC(RESET_VECTOR);
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}
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bool Core::DoState(StateWrapper& sw)
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@ -501,6 +513,12 @@ void Core::ExecuteInstruction(Instruction inst, u32 inst_pc)
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}
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break;
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case InstructionOp::xori:
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{
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WriteReg(inst.i.rt, ReadReg(inst.i.rs) ^ inst.i.imm_zext32());
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}
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break;
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case InstructionOp::addi:
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{
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const u32 old_value = ReadReg(inst.i.rs);
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@ -843,6 +861,14 @@ void Core::ExecuteCop0Instruction(Instruction inst, u32 inst_pc)
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value = m_cop0_regs.dcic.bits;
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break;
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case Cop0Reg::JUMPDEST:
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value = m_cop0_regs.JUMPDEST;
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break;
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case Cop0Reg::BadVaddr:
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value = m_cop0_regs.BadVaddr;
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break;
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case Cop0Reg::SR:
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value = m_cop0_regs.sr.bits;
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break;
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@ -855,6 +881,10 @@ void Core::ExecuteCop0Instruction(Instruction inst, u32 inst_pc)
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value = m_cop0_regs.EPC;
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break;
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case Cop0Reg::PRID:
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value = m_cop0_regs.PRID;
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break;
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default:
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Panic("Unknown COP0 reg");
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value = 0;
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