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CPU: Add missing cop0 register reads

This commit is contained in:
Connor McLaughlin 2019-09-14 13:31:44 +10:00
parent 9f36384752
commit 459db392e7
1 changed files with 32 additions and 2 deletions
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34
src/pse/cpu_core.cpp
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@ -15,14 +15,26 @@ Core::~Core() = default;
bool Core::Initialize(Bus* bus) bool Core::Initialize(Bus* bus)
{ {
m_bus = bus; m_bus = bus;
// From nocash spec.
m_cop0_regs.PRID = UINT32_C(0x00000002);
return true; return true;
} }
void Core::Reset() void Core::Reset()
{ {
m_regs = {}; m_regs = {};
m_regs.npc = RESET_VECTOR;
FetchInstruction(); m_cop0_regs.BPC = 0;
m_cop0_regs.BDA = 0;
m_cop0_regs.JUMPDEST = 0;
m_cop0_regs.BadVaddr = 0;
m_cop0_regs.BDAM = 0;
m_cop0_regs.BPCM = 0;
m_cop0_regs.EPC = 0;
SetPC(RESET_VECTOR);
} }
bool Core::DoState(StateWrapper& sw) bool Core::DoState(StateWrapper& sw)
@ -501,6 +513,12 @@ void Core::ExecuteInstruction(Instruction inst, u32 inst_pc)
} }
break; break;
case InstructionOp::xori:
{
WriteReg(inst.i.rt, ReadReg(inst.i.rs) ^ inst.i.imm_zext32());
}
break;
case InstructionOp::addi: case InstructionOp::addi:
{ {
const u32 old_value = ReadReg(inst.i.rs); const u32 old_value = ReadReg(inst.i.rs);
@ -843,6 +861,14 @@ void Core::ExecuteCop0Instruction(Instruction inst, u32 inst_pc)
value = m_cop0_regs.dcic.bits; value = m_cop0_regs.dcic.bits;
break; break;
case Cop0Reg::JUMPDEST:
value = m_cop0_regs.JUMPDEST;
break;
case Cop0Reg::BadVaddr:
value = m_cop0_regs.BadVaddr;
break;
case Cop0Reg::SR: case Cop0Reg::SR:
value = m_cop0_regs.sr.bits; value = m_cop0_regs.sr.bits;
break; break;
@ -855,6 +881,10 @@ void Core::ExecuteCop0Instruction(Instruction inst, u32 inst_pc)
value = m_cop0_regs.EPC; value = m_cop0_regs.EPC;
break; break;
case Cop0Reg::PRID:
value = m_cop0_regs.PRID;
break;
default: default:
Panic("Unknown COP0 reg"); Panic("Unknown COP0 reg");
value = 0; value = 0;