From 421bd23dc8e65f416cae87a6a3f5cc44b5c5520c Mon Sep 17 00:00:00 2001 From: Stenzek Date: Tue, 13 Aug 2024 14:48:16 +1000 Subject: [PATCH] Bus: Add stub for SIO2 accesses But only enable it when using a PS2 BIOS. I could put the check in the handler registration, but realistically this is basically never going to be called, so better to keep things simple. --- src/core/bus.cpp | 35 +++++++++++++++++++++++++++++++++++ src/core/bus.h | 5 ++++- 2 files changed, 39 insertions(+), 1 deletion(-) diff --git a/src/core/bus.cpp b/src/core/bus.cpp index 466d78eaf..c06c7356c 100644 --- a/src/core/bus.cpp +++ b/src/core/bus.cpp @@ -1087,6 +1087,8 @@ template static u32 EXP2ReadHandler(VirtualMemoryAddress template static void EXP2WriteHandler(VirtualMemoryAddress address, u32 value); template static u32 EXP3ReadHandler(VirtualMemoryAddress address); template static void EXP3WriteHandler(VirtualMemoryAddress address, u32 value); +template static u32 SIO2ReadHandler(PhysicalMemoryAddress address); +template static void SIO2WriteHandler(PhysicalMemoryAddress address, u32 value); template static u32 HardwareReadHandler(VirtualMemoryAddress address); template static void HardwareWriteHandler(VirtualMemoryAddress address, u32 value); @@ -1431,6 +1433,36 @@ void Bus::EXP3WriteHandler(VirtualMemoryAddress address, u32 value) } } +template +u32 Bus::SIO2ReadHandler(PhysicalMemoryAddress address) +{ + // Stub for using PS2 BIOS. + if (const BIOS::ImageInfo* ii = System::GetBIOSImageInfo(); + !ii || ii->fastboot_patch != BIOS::ImageInfo::FastBootPatch::Type2) [[unlikely]] + { + // Throw exception when not using PS2 BIOS. + return UnmappedReadHandler(address); + } + + WARNING_LOG("SIO2 read: 0x{:08X}", address); + return 0; +} + +template +void Bus::SIO2WriteHandler(PhysicalMemoryAddress address, u32 value) +{ + // Stub for using PS2 BIOS. + if (const BIOS::ImageInfo* ii = System::GetBIOSImageInfo(); + !ii || ii->fastboot_patch != BIOS::ImageInfo::FastBootPatch::Type2) [[unlikely]] + { + // Throw exception when not using PS2 BIOS. + UnmappedWriteHandler(address, value); + return; + } + + WARNING_LOG("SIO2 write: 0x{:08X} <- 0x{:08X}", address, value); +} + //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// // HARDWARE HANDLERS //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////// @@ -1900,6 +1932,7 @@ void Bus::SetHandlers() SET(g_memory_handlers, KUSEG | HW_BASE, HW_SIZE, HardwareReadHandler, HardwareWriteHandler); SET(g_memory_handlers, KUSEG | EXP2_BASE, EXP2_SIZE, EXP2ReadHandler, EXP2WriteHandler); SET(g_memory_handlers, KUSEG | EXP3_BASE, EXP3_SIZE, EXP3ReadHandler, EXP3WriteHandler); + SET(g_memory_handlers, KUSEG | SIO2_BASE, SIO2_SIZE, SIO2ReadHandler, SIO2WriteHandler); SET(g_memory_handlers_isc, KUSEG, 0x80000000, ICacheReadHandler, ICacheWriteHandler); // KSEG0 - Cached @@ -1910,6 +1943,7 @@ void Bus::SetHandlers() SET(g_memory_handlers, KSEG0 | HW_BASE, HW_SIZE, HardwareReadHandler, HardwareWriteHandler); SET(g_memory_handlers, KSEG0 | EXP2_BASE, EXP2_SIZE, EXP2ReadHandler, EXP2WriteHandler); SET(g_memory_handlers, KSEG0 | EXP3_BASE, EXP3_SIZE, EXP3ReadHandler, EXP3WriteHandler); + SET(g_memory_handlers, KSEG0 | SIO2_BASE, SIO2_SIZE, SIO2ReadHandler, SIO2WriteHandler); SET(g_memory_handlers_isc, KSEG0, 0x20000000, ICacheReadHandler, ICacheWriteHandler); // KSEG1 - Uncached @@ -1919,6 +1953,7 @@ void Bus::SetHandlers() SETUC(KSEG1 | HW_BASE, HW_SIZE, HardwareReadHandler, HardwareWriteHandler); SETUC(KSEG1 | EXP2_BASE, EXP2_SIZE, EXP2ReadHandler, EXP2WriteHandler); SETUC(KSEG1 | EXP3_BASE, EXP3_SIZE, EXP3ReadHandler, EXP3WriteHandler); + SETUC(KSEG1 | SIO2_BASE, SIO2_SIZE, SIO2ReadHandler, SIO2WriteHandler); // KSEG2 - Uncached - 0xFFFE0130 SETUC(KSEG2 | 0xFFFE0000, 0x1000, CacheControlReadHandler, CacheControlWriteHandler); diff --git a/src/core/bus.h b/src/core/bus.h index e6f3e7d0d..ce1088c66 100644 --- a/src/core/bus.h +++ b/src/core/bus.h @@ -67,7 +67,10 @@ enum : u32 MDEC_MASK = MDEC_SIZE - 1, SPU_BASE = 0x1F801C00, SPU_SIZE = 0x400, - SPU_MASK = 0x3FF, + SPU_MASK = SPU_SIZE - 1, + SIO2_BASE = 0x1F808000, + SIO2_SIZE = 0x1000, + SIO2_MASK = SIO2_SIZE - 1, EXP2_BASE = 0x1F802000, EXP2_SIZE = 0x2000, EXP2_MASK = EXP2_SIZE - 1,