diff --git a/src/core/bus.h b/src/core/bus.h
index de50b8287..6e126885a 100644
--- a/src/core/bus.h
+++ b/src/core/bus.h
@@ -29,6 +29,55 @@ class Bus
   friend DMA;
 
 public:
+  enum : u32
+  {
+    RAM_BASE = 0x00000000,
+    RAM_SIZE = 0x200000,
+    RAM_MASK = RAM_SIZE - 1,
+    RAM_MIRROR_END = 0x800000,
+    EXP1_BASE = 0x1F000000,
+    EXP1_SIZE = 0x800000,
+    EXP1_MASK = EXP1_SIZE - 1,
+    MEMCTRL_BASE = 0x1F801000,
+    MEMCTRL_SIZE = 0x40,
+    MEMCTRL_MASK = MEMCTRL_SIZE - 1,
+    PAD_BASE = 0x1F801040,
+    PAD_SIZE = 0x10,
+    PAD_MASK = PAD_SIZE - 1,
+    SIO_BASE = 0x1F801050,
+    SIO_SIZE = 0x10,
+    SIO_MASK = SIO_SIZE - 1,
+    MEMCTRL2_BASE = 0x1F801060,
+    MEMCTRL2_SIZE = 0x10,
+    MEMCTRL2_MASK = MEMCTRL_SIZE - 1,
+    INTERRUPT_CONTROLLER_BASE = 0x1F801070,
+    INTERRUPT_CONTROLLER_SIZE = 0x10,
+    INTERRUPT_CONTROLLER_MASK = INTERRUPT_CONTROLLER_SIZE - 1,
+    DMA_BASE = 0x1F801080,
+    DMA_SIZE = 0x80,
+    DMA_MASK = DMA_SIZE - 1,
+    TIMERS_BASE = 0x1F801100,
+    TIMERS_SIZE = 0x40,
+    TIMERS_MASK = TIMERS_SIZE - 1,
+    CDROM_BASE = 0x1F801800,
+    CDROM_SIZE = 0x10,
+    CDROM_MASK = CDROM_SIZE - 1,
+    GPU_BASE = 0x1F801810,
+    GPU_SIZE = 0x10,
+    GPU_MASK = GPU_SIZE - 1,
+    MDEC_BASE = 0x1F801820,
+    MDEC_SIZE = 0x10,
+    MDEC_MASK = MDEC_SIZE - 1,
+    SPU_BASE = 0x1F801C00,
+    SPU_SIZE = 0x400,
+    SPU_MASK = 0x3FF,
+    EXP2_BASE = 0x1F802000,
+    EXP2_SIZE = 0x2000,
+    EXP2_MASK = EXP2_SIZE - 1,
+    BIOS_BASE = 0x1FC00000,
+    BIOS_SIZE = 0x80000
+  };
+
   Bus();
   ~Bus();
 
@@ -85,56 +134,10 @@ public:
   /// Clears all code bits for RAM regions.
   ALWAYS_INLINE void ClearRAMCodePageFlags() { m_ram_code_bits.reset(); }
 
-private:
-  enum : u32
-  {
-    RAM_BASE = 0x00000000,
-    RAM_SIZE = 0x200000,
-    RAM_MASK = RAM_SIZE - 1,
-    RAM_MIRROR_END = 0x800000,
-    EXP1_BASE = 0x1F000000,
-    EXP1_SIZE = 0x800000,
-    EXP1_MASK = EXP1_SIZE - 1,
-    MEMCTRL_BASE = 0x1F801000,
-    MEMCTRL_SIZE = 0x40,
-    MEMCTRL_MASK = MEMCTRL_SIZE - 1,
-    PAD_BASE = 0x1F801040,
-    PAD_SIZE = 0x10,
-    PAD_MASK = PAD_SIZE - 1,
-    SIO_BASE = 0x1F801050,
-    SIO_SIZE = 0x10,
-    SIO_MASK = SIO_SIZE - 1,
-    MEMCTRL2_BASE = 0x1F801060,
-    MEMCTRL2_SIZE = 0x10,
-    MEMCTRL2_MASK = MEMCTRL_SIZE - 1,
-    INTERRUPT_CONTROLLER_BASE = 0x1F801070,
-    INTERRUPT_CONTROLLER_SIZE = 0x10,
-    INTERRUPT_CONTROLLER_MASK = INTERRUPT_CONTROLLER_SIZE - 1,
-    DMA_BASE = 0x1F801080,
-    DMA_SIZE = 0x80,
-    DMA_MASK = DMA_SIZE - 1,
-    TIMERS_BASE = 0x1F801100,
-    TIMERS_SIZE = 0x40,
-    TIMERS_MASK = TIMERS_SIZE - 1,
-    CDROM_BASE = 0x1F801800,
-    CDROM_SIZE = 0x10,
-    CDROM_MASK = CDROM_SIZE - 1,
-    GPU_BASE = 0x1F801810,
-    GPU_SIZE = 0x10,
-    GPU_MASK = GPU_SIZE - 1,
-    MDEC_BASE = 0x1F801820,
-    MDEC_SIZE = 0x10,
-    MDEC_MASK = MDEC_SIZE - 1,
-    SPU_BASE = 0x1F801C00,
-    SPU_SIZE = 0x400,
-    SPU_MASK = 0x3FF,
-    EXP2_BASE = 0x1F802000,
-    EXP2_SIZE = 0x2000,
-    EXP2_MASK = EXP2_SIZE - 1,
-    BIOS_BASE = 0x1FC00000,
-    BIOS_SIZE = 0x80000
-  };
+  /// Direct access to RAM - used by DMA.
+  ALWAYS_INLINE u8* GetRAM() { return m_ram; }
 
+private:
   enum : u32
   {
     MEMCTRL_REG_COUNT = 9
@@ -238,9 +241,6 @@ private:
 
   void DoInvalidateCodeCache(u32 page_index);
 
-  /// Direct access to RAM - used by DMA.
-  ALWAYS_INLINE u8* GetRAM() { return m_ram; }
-
   /// Returns the number of cycles stolen by DMA RAM access.
   ALWAYS_INLINE static TickCount GetDMARAMTickCount(u32 word_count)
   {