CPU/NewRec: Handle mtc0 rt, sr
This commit is contained in:
parent
0ba50243ec
commit
312790c9a6
data/resources
src/core
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@ -200045,7 +200045,6 @@
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}
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],
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"traits": {
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"ForceInterpreter": true,
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"IsLibCryptProtected": true
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}
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},
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@ -200084,11 +200083,7 @@
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}
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],
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"compatibility": {
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"rating": 5,
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"comments": "Must use interpreter to avoid crash"
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},
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"traits": {
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"ForceInterpreter": true
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"rating": 5
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}
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},
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{
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@ -2357,6 +2357,13 @@ void CPU::CodeCache::InterpretUncachedBlock()
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{
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break;
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}
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else if ((g_state.current_instruction.bits & 0xFFC0FFFFu) == 0x40806000u && HasPendingInterrupt())
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{
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// mtc0 rt, sr - Jackie Chan Stuntmaster, MTV Sports games.
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// Pain in the ass games trigger a software interrupt by writing to SR.Im.
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break;
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}
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in_branch_delay_slot = branch;
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}
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@ -367,14 +367,14 @@ void CPU::NewRec::AArch32Compiler::EndBlock(const std::optional<u32>& newpc, boo
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// flush regs
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Flush(FLUSH_END_BLOCK);
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EndAndLinkBlock(newpc, do_event_test);
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EndAndLinkBlock(newpc, do_event_test, false);
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}
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void CPU::NewRec::AArch32Compiler::EndBlockWithException(Exception excode)
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{
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// flush regs, but not pc, it's going to get overwritten
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// flush cycles because of the GTE instruction stuff...
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Flush(FLUSH_END_BLOCK | FLUSH_FOR_EXCEPTION);
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Flush(FLUSH_END_BLOCK | FLUSH_FOR_EXCEPTION | FLUSH_FOR_C_CALL);
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// TODO: flush load delay
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// TODO: break for pcdrv
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@ -385,14 +385,16 @@ void CPU::NewRec::AArch32Compiler::EndBlockWithException(Exception excode)
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EmitCall(reinterpret_cast<const void*>(static_cast<void (*)(u32, u32)>(&CPU::RaiseException)));
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m_dirty_pc = false;
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EndAndLinkBlock(std::nullopt, true);
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EndAndLinkBlock(std::nullopt, true, false);
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}
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void CPU::NewRec::AArch32Compiler::EndAndLinkBlock(const std::optional<u32>& newpc, bool do_event_test)
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void CPU::NewRec::AArch32Compiler::EndAndLinkBlock(const std::optional<u32>& newpc, bool do_event_test,
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bool force_run_events)
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{
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// event test
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// pc should've been flushed
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DebugAssert(!m_dirty_pc);
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DebugAssert(!m_dirty_pc && !force_run_events);
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m_block_ended = true;
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// TODO: try extracting this to a function
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@ -420,7 +422,11 @@ void CPU::NewRec::AArch32Compiler::EndAndLinkBlock(const std::optional<u32>& new
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armEmitCondBranch(armAsm, ge, CodeCache::g_run_events_and_dispatch);
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// jump to dispatcher or next block
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if (!newpc.has_value())
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if (force_run_events)
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{
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armEmitJmp(armAsm, CodeCache::g_run_events_and_dispatch, false);
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}
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else if (!newpc.has_value())
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{
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armEmitJmp(armAsm, CodeCache::g_dispatcher, false);
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}
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@ -438,8 +444,6 @@ void CPU::NewRec::AArch32Compiler::EndAndLinkBlock(const std::optional<u32>& new
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armEmitJmp(armAsm, target, true);
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}
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}
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m_block_ended = true;
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}
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const void* CPU::NewRec::AArch32Compiler::EndCompile(u32* code_size, u32* far_code_size)
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@ -1979,9 +1983,31 @@ void CPU::NewRec::AArch32Compiler::TestInterrupts(const vixl::aarch32::Register&
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SwitchToFarCode(true, ne);
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BackupHostState();
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Flush(FLUSH_FLUSH_MIPS_REGISTERS | FLUSH_FOR_EXCEPTION | FLUSH_FOR_C_CALL);
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EmitCall(reinterpret_cast<const void*>(&DispatchInterrupt));
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EndBlock(std::nullopt, true);
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Flush(FLUSH_END_BLOCK | FLUSH_FOR_EXCEPTION | FLUSH_FOR_C_CALL);
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// Can't use EndBlockWithException() here, because it'll use the wrong PC.
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// Can't use RaiseException() on the fast path if we're the last instruction, because the next PC is unknown.
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if (!iinfo->is_last_instruction)
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{
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EmitMov(RARG1, Cop0Registers::CAUSE::MakeValueForException(Exception::INT, iinfo->is_branch_instruction, false,
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(inst + 1)->cop.cop_n));
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EmitMov(RARG2, m_compiler_pc);
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EmitCall(reinterpret_cast<const void*>(static_cast<void (*)(u32, u32)>(&CPU::RaiseException)));
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m_dirty_pc = false;
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EndAndLinkBlock(std::nullopt, true, false);
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}
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else
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{
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EmitMov(RARG1, 0);
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if (m_dirty_pc)
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EmitMov(RARG2, m_compiler_pc);
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armAsm->str(RARG1, PTR(&g_state.downcount));
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if (m_dirty_pc)
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armAsm->str(RARG2, m_compiler_pc);
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m_dirty_pc = false;
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EndAndLinkBlock(std::nullopt, false, true);
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}
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RestoreHostState();
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SwitchToNearCode(false);
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@ -35,7 +35,7 @@ protected:
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void GenerateCall(const void* func, s32 arg1reg = -1, s32 arg2reg = -1, s32 arg3reg = -1) override;
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void EndBlock(const std::optional<u32>& newpc, bool do_event_test) override;
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void EndBlockWithException(Exception excode) override;
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void EndAndLinkBlock(const std::optional<u32>& newpc, bool do_event_test);
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void EndAndLinkBlock(const std::optional<u32>& newpc, bool do_event_test, bool force_run_events);
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const void* EndCompile(u32* code_size, u32* far_code_size) override;
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void Flush(u32 flags) override;
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@ -339,14 +339,14 @@ void CPU::NewRec::AArch64Compiler::EndBlock(const std::optional<u32>& newpc, boo
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// flush regs
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Flush(FLUSH_END_BLOCK);
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EndAndLinkBlock(newpc, do_event_test);
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EndAndLinkBlock(newpc, do_event_test, false);
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}
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void CPU::NewRec::AArch64Compiler::EndBlockWithException(Exception excode)
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{
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// flush regs, but not pc, it's going to get overwritten
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// flush cycles because of the GTE instruction stuff...
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Flush(FLUSH_END_BLOCK | FLUSH_FOR_EXCEPTION);
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Flush(FLUSH_END_BLOCK | FLUSH_FOR_EXCEPTION | FLUSH_FOR_C_CALL);
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// TODO: flush load delay
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// TODO: break for pcdrv
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@ -357,14 +357,16 @@ void CPU::NewRec::AArch64Compiler::EndBlockWithException(Exception excode)
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EmitCall(reinterpret_cast<const void*>(static_cast<void (*)(u32, u32)>(&CPU::RaiseException)));
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m_dirty_pc = false;
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EndAndLinkBlock(std::nullopt, true);
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EndAndLinkBlock(std::nullopt, true, false);
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}
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void CPU::NewRec::AArch64Compiler::EndAndLinkBlock(const std::optional<u32>& newpc, bool do_event_test)
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void CPU::NewRec::AArch64Compiler::EndAndLinkBlock(const std::optional<u32>& newpc, bool do_event_test,
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bool force_run_events)
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{
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// event test
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// pc should've been flushed
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DebugAssert(!m_dirty_pc);
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DebugAssert(!m_dirty_pc && !m_block_ended);
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m_block_ended = true;
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// TODO: try extracting this to a function
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armEmitCondBranch(armAsm, ge, CodeCache::g_run_events_and_dispatch);
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// jump to dispatcher or next block
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if (!newpc.has_value())
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if (force_run_events)
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{
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armEmitJmp(armAsm, CodeCache::g_run_events_and_dispatch, false);
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}
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else if (!newpc.has_value())
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{
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armEmitJmp(armAsm, CodeCache::g_dispatcher, false);
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}
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armEmitJmp(armAsm, target, true);
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}
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}
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m_block_ended = true;
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}
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const void* CPU::NewRec::AArch64Compiler::EndCompile(u32* code_size, u32* far_code_size)
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@ -1953,9 +1957,29 @@ void CPU::NewRec::AArch64Compiler::TestInterrupts(const vixl::aarch64::WRegister
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SwitchToFarCode(true, ne);
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BackupHostState();
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Flush(FLUSH_FLUSH_MIPS_REGISTERS | FLUSH_FOR_EXCEPTION | FLUSH_FOR_C_CALL);
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EmitCall(reinterpret_cast<const void*>(&DispatchInterrupt));
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EndBlock(std::nullopt, true);
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Flush(FLUSH_END_BLOCK | FLUSH_FOR_EXCEPTION | FLUSH_FOR_C_CALL);
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// Can't use EndBlockWithException() here, because it'll use the wrong PC.
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// Can't use RaiseException() on the fast path if we're the last instruction, because the next PC is unknown.
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if (!iinfo->is_last_instruction)
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{
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EmitMov(RWARG1, Cop0Registers::CAUSE::MakeValueForException(Exception::INT, iinfo->is_branch_instruction, false,
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(inst + 1)->cop.cop_n));
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EmitMov(RWARG2, m_compiler_pc);
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EmitCall(reinterpret_cast<const void*>(static_cast<void (*)(u32, u32)>(&CPU::RaiseException)));
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EndAndLinkBlock(std::nullopt, true, false);
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}
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else
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{
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if (m_dirty_pc)
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EmitMov(RWARG1, m_compiler_pc);
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armAsm->str(wzr, PTR(&g_state.downcount));
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if (m_dirty_pc)
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armAsm->str(RWARG1, PTR(&g_state.pc));
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m_dirty_pc = false;
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EndAndLinkBlock(std::nullopt, false, true);
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}
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RestoreHostState();
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SwitchToNearCode(false);
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@ -34,7 +34,7 @@ protected:
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void GenerateCall(const void* func, s32 arg1reg = -1, s32 arg2reg = -1, s32 arg3reg = -1) override;
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void EndBlock(const std::optional<u32>& newpc, bool do_event_test) override;
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void EndBlockWithException(Exception excode) override;
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void EndAndLinkBlock(const std::optional<u32>& newpc, bool do_event_test);
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void EndAndLinkBlock(const std::optional<u32>& newpc, bool do_event_test, bool force_run_events);
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const void* EndCompile(u32* code_size, u32* far_code_size) override;
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void Flush(u32 flags) override;
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@ -586,14 +586,14 @@ void CPU::NewRec::RISCV64Compiler::EndBlock(const std::optional<u32>& newpc, boo
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// flush regs
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Flush(FLUSH_END_BLOCK);
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EndAndLinkBlock(newpc, do_event_test);
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EndAndLinkBlock(newpc, do_event_test, false);
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}
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void CPU::NewRec::RISCV64Compiler::EndBlockWithException(Exception excode)
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{
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// flush regs, but not pc, it's going to get overwritten
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// flush cycles because of the GTE instruction stuff...
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Flush(FLUSH_END_BLOCK | FLUSH_FOR_EXCEPTION);
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Flush(FLUSH_END_BLOCK | FLUSH_FOR_EXCEPTION | FLUSH_FOR_C_CALL);
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// TODO: flush load delay
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// TODO: break for pcdrv
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@ -604,14 +604,16 @@ void CPU::NewRec::RISCV64Compiler::EndBlockWithException(Exception excode)
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EmitCall(reinterpret_cast<const void*>(static_cast<void (*)(u32, u32)>(&CPU::RaiseException)));
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m_dirty_pc = false;
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EndAndLinkBlock(std::nullopt, true);
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EndAndLinkBlock(std::nullopt, true, false);
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}
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void CPU::NewRec::RISCV64Compiler::EndAndLinkBlock(const std::optional<u32>& newpc, bool do_event_test)
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void CPU::NewRec::RISCV64Compiler::EndAndLinkBlock(const std::optional<u32>& newpc, bool do_event_test,
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bool force_run_events)
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{
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// event test
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// pc should've been flushed
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DebugAssert(!m_dirty_pc);
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DebugAssert(!m_dirty_pc && !m_block_ended);
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m_block_ended = true;
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// TODO: try extracting this to a function
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// TODO: move the cycle flush in here..
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@ -646,7 +648,11 @@ void CPU::NewRec::RISCV64Compiler::EndAndLinkBlock(const std::optional<u32>& new
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}
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// jump to dispatcher or next block
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if (!newpc.has_value())
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if (force_run_events)
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{
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rvEmitJmp(rvAsm, CodeCache::g_run_events_and_dispatch);
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}
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else if (!newpc.has_value())
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{
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rvEmitJmp(rvAsm, CodeCache::g_dispatcher);
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}
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@ -664,8 +670,6 @@ void CPU::NewRec::RISCV64Compiler::EndAndLinkBlock(const std::optional<u32>& new
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rvEmitJmp(rvAsm, target);
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}
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}
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m_block_ended = true;
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}
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const void* CPU::NewRec::RISCV64Compiler::EndCompile(u32* code_size, u32* far_code_size)
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@ -2209,9 +2213,29 @@ void CPU::NewRec::RISCV64Compiler::TestInterrupts(const biscuit::GPR& sr)
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rvAsm->ANDI(sr, sr, 0xFF);
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SwitchToFarCode(true, &Assembler::BEQ, sr, zero);
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BackupHostState();
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Flush(FLUSH_FLUSH_MIPS_REGISTERS | FLUSH_FOR_EXCEPTION | FLUSH_FOR_C_CALL);
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EmitCall(reinterpret_cast<const void*>(&DispatchInterrupt));
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EndBlock(std::nullopt, true);
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Flush(FLUSH_END_BLOCK | FLUSH_FOR_EXCEPTION | FLUSH_FOR_C_CALL);
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// Can't use EndBlockWithException() here, because it'll use the wrong PC.
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// Can't use RaiseException() on the fast path if we're the last instruction, because the next PC is unknown.
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if (!iinfo->is_last_instruction)
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{
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EmitMov(RARG1, Cop0Registers::CAUSE::MakeValueForException(Exception::INT, iinfo->is_branch_instruction, false,
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(inst + 1)->cop.cop_n));
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EmitMov(RARG2, m_compiler_pc);
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EmitCall(reinterpret_cast<const void*>(static_cast<void (*)(u32, u32)>(&CPU::RaiseException)));
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EndAndLinkBlock(std::nullopt, true, false);
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}
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else
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{
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if (m_dirty_pc)
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EmitMov(RARG1, m_compiler_pc);
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rvAsm->SW(biscuit::zero, PTR(&g_state.downcount));
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if (m_dirty_pc)
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rvAsm->SW(RARG1, PTR(&g_state.pc));
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m_dirty_pc = false;
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EndAndLinkBlock(std::nullopt, false, true);
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}
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RestoreHostState();
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SwitchToNearCode(false);
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@ -31,7 +31,7 @@ protected:
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void GenerateCall(const void* func, s32 arg1reg = -1, s32 arg2reg = -1, s32 arg3reg = -1) override;
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void EndBlock(const std::optional<u32>& newpc, bool do_event_test) override;
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void EndBlockWithException(Exception excode) override;
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void EndAndLinkBlock(const std::optional<u32>& newpc, bool do_event_test);
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void EndAndLinkBlock(const std::optional<u32>& newpc, bool do_event_test, bool force_run_events);
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const void* EndCompile(u32* code_size, u32* far_code_size) override;
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void Flush(u32 flags) override;
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@ -222,14 +222,14 @@ void CPU::NewRec::X64Compiler::EndBlock(const std::optional<u32>& newpc, bool do
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// flush regs
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Flush(FLUSH_END_BLOCK);
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EndAndLinkBlock(newpc, do_event_test);
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EndAndLinkBlock(newpc, do_event_test, false);
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}
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void CPU::NewRec::X64Compiler::EndBlockWithException(Exception excode)
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{
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// flush regs, but not pc, it's going to get overwritten
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// flush cycles because of the GTE instruction stuff...
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Flush(FLUSH_END_BLOCK | FLUSH_FOR_EXCEPTION);
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Flush(FLUSH_END_BLOCK | FLUSH_FOR_EXCEPTION | FLUSH_FOR_C_CALL);
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// TODO: flush load delay
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// TODO: break for pcdrv
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@ -240,14 +240,16 @@ void CPU::NewRec::X64Compiler::EndBlockWithException(Exception excode)
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cg->call(static_cast<void (*)(u32, u32)>(&CPU::RaiseException));
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m_dirty_pc = false;
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EndAndLinkBlock(std::nullopt, true);
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EndAndLinkBlock(std::nullopt, true, false);
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}
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void CPU::NewRec::X64Compiler::EndAndLinkBlock(const std::optional<u32>& newpc, bool do_event_test)
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void CPU::NewRec::X64Compiler::EndAndLinkBlock(const std::optional<u32>& newpc, bool do_event_test,
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bool force_run_events)
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{
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// event test
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// pc should've been flushed
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DebugAssert(!m_dirty_pc);
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DebugAssert(!m_dirty_pc && !m_block_ended);
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m_block_ended = true;
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// TODO: try extracting this to a function
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@ -261,6 +263,12 @@ void CPU::NewRec::X64Compiler::EndAndLinkBlock(const std::optional<u32>& newpc,
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cg->inc(cg->dword[PTR(&g_state.pending_ticks)]);
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else if (cycles > 0)
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cg->add(cg->dword[PTR(&g_state.pending_ticks)], cycles);
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if (force_run_events)
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{
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cg->jmp(CodeCache::g_run_events_and_dispatch);
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return;
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}
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}
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else
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{
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@ -303,8 +311,6 @@ void CPU::NewRec::X64Compiler::EndAndLinkBlock(const std::optional<u32>& newpc,
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cg->jmp(target, CodeGenerator::T_NEAR);
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}
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}
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m_block_ended = true;
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}
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const void* CPU::NewRec::X64Compiler::EndCompile(u32* code_size, u32* far_code_size)
|
||||
|
@ -1339,7 +1345,7 @@ Xbyak::Reg32 CPU::NewRec::X64Compiler::GenerateLoad(const Xbyak::Reg32& addr_reg
|
|||
cg->mov(RWARG2, m_current_instruction_pc);
|
||||
cg->call(static_cast<void (*)(u32, u32)>(&CPU::RaiseException));
|
||||
m_dirty_pc = false;
|
||||
EndAndLinkBlock(std::nullopt, true);
|
||||
EndAndLinkBlock(std::nullopt, true, false);
|
||||
|
||||
SwitchToNearCode(false);
|
||||
RestoreHostState();
|
||||
|
@ -1459,7 +1465,7 @@ void CPU::NewRec::X64Compiler::GenerateStore(const Xbyak::Reg32& addr_reg, const
|
|||
cg->mov(RWARG2, m_current_instruction_pc);
|
||||
cg->call(reinterpret_cast<const void*>(static_cast<void (*)(u32, u32)>(&CPU::RaiseException)));
|
||||
m_dirty_pc = false;
|
||||
EndAndLinkBlock(std::nullopt, true);
|
||||
EndAndLinkBlock(std::nullopt, true, false);
|
||||
|
||||
SwitchToNearCode(false);
|
||||
RestoreHostState();
|
||||
|
@ -1929,9 +1935,28 @@ void CPU::NewRec::X64Compiler::TestInterrupts(const Xbyak::Reg32& sr)
|
|||
|
||||
SwitchToFarCode(true, &CodeGenerator::jnz);
|
||||
BackupHostState();
|
||||
Flush(FLUSH_FLUSH_MIPS_REGISTERS | FLUSH_FOR_EXCEPTION | FLUSH_FOR_C_CALL);
|
||||
cg->call(reinterpret_cast<const void*>(&DispatchInterrupt));
|
||||
EndBlock(std::nullopt, true);
|
||||
Flush(FLUSH_END_BLOCK | FLUSH_FOR_EXCEPTION | FLUSH_FOR_C_CALL);
|
||||
|
||||
// Can't use EndBlockWithException() here, because it'll use the wrong PC.
|
||||
// Can't use RaiseException() on the fast path if we're the last instruction, because the next PC is unknown.
|
||||
if (!iinfo->is_last_instruction)
|
||||
{
|
||||
cg->mov(RWARG1, Cop0Registers::CAUSE::MakeValueForException(Exception::INT, iinfo->is_branch_instruction, false,
|
||||
(inst + 1)->cop.cop_n));
|
||||
cg->mov(RWARG2, m_compiler_pc);
|
||||
cg->call(static_cast<void (*)(u32, u32)>(&CPU::RaiseException));
|
||||
m_dirty_pc = false;
|
||||
EndAndLinkBlock(std::nullopt, true, false);
|
||||
}
|
||||
else
|
||||
{
|
||||
if (m_dirty_pc)
|
||||
cg->mov(cg->dword[PTR(&g_state.pc)], m_compiler_pc);
|
||||
m_dirty_pc = false;
|
||||
cg->mov(cg->dword[PTR(&g_state.downcount)], 0);
|
||||
EndAndLinkBlock(std::nullopt, false, true);
|
||||
}
|
||||
|
||||
RestoreHostState();
|
||||
SwitchToNearCode(false);
|
||||
|
||||
|
|
|
@ -33,7 +33,7 @@ protected:
|
|||
void GenerateCall(const void* func, s32 arg1reg = -1, s32 arg2reg = -1, s32 arg3reg = -1) override;
|
||||
void EndBlock(const std::optional<u32>& newpc, bool do_event_test) override;
|
||||
void EndBlockWithException(Exception excode) override;
|
||||
void EndAndLinkBlock(const std::optional<u32>& newpc, bool do_event_test);
|
||||
void EndAndLinkBlock(const std::optional<u32>& newpc, bool do_event_test, bool force_run_events);
|
||||
const void* EndCompile(u32* code_size, u32* far_code_size) override;
|
||||
|
||||
void Flush(u32 flags) override;
|
||||
|
|
|
@ -2740,7 +2740,14 @@ bool CodeGenerator::Compile_cop0(Instruction instruction, const CodeCache::Instr
|
|||
EmitAnd(sr_value.host_reg, sr_value.host_reg, cause_value);
|
||||
EmitTest(sr_value.host_reg, Value::FromConstantU32(0xFF00));
|
||||
EmitConditionalBranch(Condition::Zero, false, &no_interrupt);
|
||||
|
||||
EmitBranch(GetCurrentFarCodePointer());
|
||||
SwitchToFarCode();
|
||||
WriteNewPC(CalculatePC(), false);
|
||||
EmitStoreCPUStructField(offsetof(State, downcount), Value::FromConstantU32(0));
|
||||
EmitExceptionExit();
|
||||
SwitchToNearCode();
|
||||
|
||||
EmitBindLabel(&no_interrupt);
|
||||
m_register_cache.UninhibitAllocation();
|
||||
}
|
||||
|
|
Loading…
Reference in New Issue