DMA: Properly handle bus errors and DICR transitions
This commit is contained in:
Stenzek
parent
fa6850902a
commit
2003c9452b
254
src/core/dma.cpp
254
src/core/dma.cpp
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@ -42,7 +42,8 @@ enum class SyncMode : u32
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};
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static constexpr PhysicalMemoryAddress BASE_ADDRESS_MASK = UINT32_C(0x00FFFFFF);
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// static constexpr PhysicalMemoryAddress ADDRESS_MASK = UINT32_C(0x001FFFFC);
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static constexpr PhysicalMemoryAddress TRANSFER_ADDRESS_MASK = UINT32_C(0x00FFFFFC);
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static constexpr PhysicalMemoryAddress LINKED_LIST_TERMINATOR = UINT32_C(0x00FFFFFF);
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struct ChannelState
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{
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@ -119,7 +120,7 @@ union DICR
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{
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u32 bits;
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BitField<u32, bool, 15, 1> force_irq;
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BitField<u32, bool, 15, 1> bus_error;
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BitField<u32, bool, 16, 1> MDECin_irq_enable;
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BitField<u32, bool, 17, 1> MDECout_irq_enable;
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BitField<u32, bool, 18, 1> GPU_irq_enable;
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@ -137,27 +138,33 @@ union DICR
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BitField<u32, bool, 30, 1> OTC_irq_flag;
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BitField<u32, bool, 31, 1> master_flag;
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ALWAYS_INLINE bool IsIRQEnabled(Channel channel) const
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ALWAYS_INLINE bool GetIRQEnabled(Channel channel) const
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{
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return ConvertToBoolUnchecked((bits >> (static_cast<u8>(channel) + 16)) & u32(1));
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return ConvertToBoolUnchecked((bits >> (static_cast<u8>(channel) + 16)) & 1u);
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}
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ALWAYS_INLINE bool GetIRQFlag(Channel channel) const
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{
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return ConvertToBoolUnchecked((bits >> (static_cast<u8>(channel) + 24)) & u32(1));
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return ConvertToBoolUnchecked((bits >> (static_cast<u8>(channel) + 24)) & 1u);
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}
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ALWAYS_INLINE void SetIRQFlag(Channel channel) { bits |= (u32(1) << (static_cast<u8>(channel) + 24)); }
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ALWAYS_INLINE void ClearIRQFlag(Channel channel) { bits &= ~(u32(1) << (static_cast<u8>(channel) + 24)); }
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ALWAYS_INLINE void SetIRQFlag(Channel channel) { bits |= (1u << (static_cast<u8>(channel) + 24)); }
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ALWAYS_INLINE bool ShouldSetIRQFlag(Channel channel)
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{
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// bus errors trigger IRQ unconditionally, completion requires the master flag to be enabled
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return ConvertToBoolUnchecked(((bits >> (static_cast<u8>(channel) + 16)) & ((bits >> 23) & 1u)));
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}
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ALWAYS_INLINE void UpdateMasterFlag()
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{
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master_flag = master_enable && ((((bits >> 16) & u32(0b1111111)) & ((bits >> 24) & u32(0b1111111))) != 0);
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master_flag =
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(((bits & (1u << 15)) != 0u) || // bus error, or
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(((bits & (1u << 23)) != 0u) != 0u && (bits & (0b1111111u << 24)) != 0u)); // master enable + irq on any channel
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}
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};
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} // namespace
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static u32 GetAddressMask();
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static void ClearState();
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// is everything enabled for a channel to operate?
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@ -175,6 +182,10 @@ static void UnhaltTransfer(void*, TickCount ticks, TickCount ticks_late);
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template<Channel channel>
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static bool TransferChannel();
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static bool IsLinkedListTerminator(PhysicalMemoryAddress address);
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static bool CheckForBusError(Channel channel, ChannelState& cs, PhysicalMemoryAddress address, u32 size);
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static void CompleteTransfer(Channel channel, ChannelState& cs);
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// from device -> memory
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template<Channel channel>
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static TickCount TransferDeviceToMemory(u32 address, u32 increment, u32 word_count);
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@ -183,6 +194,8 @@ static TickCount TransferDeviceToMemory(u32 address, u32 increment, u32 word_cou
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template<Channel channel>
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static TickCount TransferMemoryToDevice(u32 address, u32 increment, u32 word_count);
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// configuration
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static TickCount s_max_slice_ticks = 1000;
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static TickCount s_halt_ticks = 100;
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@ -219,17 +232,11 @@ struct fmt::formatter<DMA::Channel> : fmt::formatter<fmt::string_view>
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}
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};
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u32 DMA::GetAddressMask()
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{
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return Bus::g_ram_mask & 0xFFFFFFFCu;
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}
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void DMA::Initialize()
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{
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s_max_slice_ticks = g_settings.dma_max_slice_ticks;
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s_halt_ticks = g_settings.dma_halt_ticks;
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s_transfer_buffer.resize(32);
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s_unhalt_event =
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TimingEvents::CreateTimingEvent("DMA Transfer Unhalt", 1, s_max_slice_ticks, &DMA::UnhaltTransfer, nullptr, false);
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Reset();
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@ -300,17 +307,20 @@ u32 DMA::ReadRegister(u32 offset)
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{
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case 0x00:
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{
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Log_TracePrintf("DMA%u base address -> 0x%08X", channel_index, s_state[channel_index].base_address);
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Log_TraceFmt("DMA[{}] base address -> 0x{:08X}", static_cast<Channel>(channel_index),
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s_state[channel_index].base_address);
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return s_state[channel_index].base_address;
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}
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case 0x04:
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{
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Log_TracePrintf("DMA%u block control -> 0x%08X", channel_index, s_state[channel_index].block_control.bits);
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Log_TraceFmt("DMA[{}] block control -> 0x{:08X}", static_cast<Channel>(channel_index),
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s_state[channel_index].block_control.bits);
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return s_state[channel_index].block_control.bits;
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}
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case 0x08:
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{
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Log_TracePrintf("DMA%u channel control -> 0x%08X", channel_index, s_state[channel_index].channel_control.bits);
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Log_TraceFmt("DMA[{}] channel control -> 0x{:08X}", static_cast<Channel>(channel_index),
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s_state[channel_index].channel_control.bits);
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return s_state[channel_index].channel_control.bits;
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}
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default:
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@ -321,17 +331,17 @@ u32 DMA::ReadRegister(u32 offset)
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{
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if (offset == 0x70)
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{
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Log_TracePrintf("DPCR -> 0x%08X", s_DPCR.bits);
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Log_TraceFmt("DPCR -> 0x{:08X}", s_DPCR.bits);
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return s_DPCR.bits;
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}
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else if (offset == 0x74)
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{
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Log_TracePrintf("DPCR -> 0x%08X", s_DPCR.bits);
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Log_TraceFmt("DICR -> 0x{:08X}", s_DICR.bits);
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return s_DICR.bits;
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}
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}
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Log_ErrorPrintf("Unhandled register read: %02X", offset);
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Log_ErrorFmt("Unhandled register read: {:02X}", offset);
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return UINT32_C(0xFFFFFFFF);
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}
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@ -367,7 +377,7 @@ void DMA::WriteRegister(u32 offset, u32 value)
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state.channel_control.bits = (state.channel_control.bits & ~ChannelState::ChannelControl::WRITE_MASK) |
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(value & ChannelState::ChannelControl::WRITE_MASK);
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Log_TracePrintf("DMA channel {} channel control <- 0x{:08X}", static_cast<Channel>(channel_index),
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Log_TraceFmt("DMA channel {} channel control <- 0x{:08X}", static_cast<Channel>(channel_index),
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state.channel_control.bits);
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// start/trigger bit must be enabled for OTC
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@ -416,7 +426,7 @@ void DMA::WriteRegister(u32 offset, u32 value)
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{
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case 0x70:
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{
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Log_TracePrintf("DPCR <- 0x%08X", value);
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Log_TraceFmt("DPCR <- 0x{:08X}", value);
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s_DPCR.bits = value;
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for (u32 i = 0; i < NUM_CHANNELS; i++)
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@ -433,7 +443,7 @@ void DMA::WriteRegister(u32 offset, u32 value)
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case 0x74:
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{
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Log_TracePrintf("DCIR <- 0x%08X", value);
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Log_TraceFmt("DICR <- 0x{:08X}", value);
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s_DICR.bits = (s_DICR.bits & ~DICR_WRITE_MASK) | (value & DICR_WRITE_MASK);
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s_DICR.bits = s_DICR.bits & ~(value & DICR_RESET_MASK);
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UpdateIRQ();
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@ -445,7 +455,7 @@ void DMA::WriteRegister(u32 offset, u32 value)
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}
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}
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Log_ErrorPrintf("Unhandled register write: %02X <- %08X", offset, value);
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Log_ErrorFmt("Unhandled register write: {:02X} <- {:08X}", offset, value);
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}
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void DMA::SetRequest(Channel channel, bool request)
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@ -491,20 +501,58 @@ bool DMA::IsTransferHalted()
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void DMA::UpdateIRQ()
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{
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[[maybe_unused]] const auto old_dicr = s_DICR;
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s_DICR.UpdateMasterFlag();
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if (s_DICR.master_flag)
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if (!old_dicr.master_flag && s_DICR.master_flag)
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Log_TracePrintf("Firing DMA master interrupt");
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InterruptController::SetLineState(InterruptController::IRQ::DMA, s_DICR.master_flag);
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}
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ALWAYS_INLINE_RELEASE bool DMA::IsLinkedListTerminator(PhysicalMemoryAddress address)
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{
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return ((address & LINKED_LIST_TERMINATOR) == LINKED_LIST_TERMINATOR);
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}
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ALWAYS_INLINE_RELEASE bool DMA::CheckForBusError(Channel channel, ChannelState& cs, PhysicalMemoryAddress address,
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u32 size)
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{
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// Relying on a transfer partially happening at the end of RAM, then hitting a bus error would be pretty silly.
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if ((address + size) > Bus::RAM_8MB_SIZE) [[unlikely]]
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{
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Log_DebugFmt("DMA bus error on channel {} at address 0x{:08X} size {}", channel, address, size);
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cs.channel_control.enable_busy = false;
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s_DICR.bus_error = true;
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s_DICR.SetIRQFlag(channel);
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UpdateIRQ();
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return true;
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}
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return false;
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}
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ALWAYS_INLINE_RELEASE void DMA::CompleteTransfer(Channel channel, ChannelState& cs)
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{
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// start/busy bit is cleared on end of transfer
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Log_DebugFmt("DMA transfer for channel {} complete", channel);
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cs.channel_control.enable_busy = false;
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if (s_DICR.ShouldSetIRQFlag(channel))
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{
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Log_DebugFmt("Setting DMA interrupt for channel {}", channel);
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s_DICR.SetIRQFlag(channel);
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UpdateIRQ();
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}
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}
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// Plenty of games seem to suffer from this issue where they have a linked list DMA going while polling the
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// controller. Using a too-large slice size will result in the serial timing being off, and the game thinking
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// the controller is disconnected. So we don't hurt performance too much for the general case, we reduce this
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// to equal CPU and DMA time when the controller is transferring, but otherwise leave it at the higher size.
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enum : u32
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enum : TickCount
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{
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SLICE_SIZE_WHEN_TRANSMITTING_PAD = 100,
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HALT_TICKS_WHEN_TRANSMITTING_PAD = 100
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HALT_TICKS_WHEN_TRANSMITTING_PAD = 100,
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LINKED_LIST_HEADER_READ_TICKS = 10,
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LINKED_LIST_BLOCK_SETUP_TICKS = 5,
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};
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TickCount DMA::GetTransferSliceTicks()
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@ -529,7 +577,6 @@ template<DMA::Channel channel>
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bool DMA::TransferChannel()
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{
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ChannelState& cs = s_state[static_cast<u32>(channel)];
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const u32 mask = GetAddressMask();
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const bool copy_to_device = cs.channel_control.copy_to_device;
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@ -543,18 +590,23 @@ bool DMA::TransferChannel()
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case SyncMode::Manual:
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{
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const u32 word_count = cs.block_control.manual.GetWordCount();
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Log_DebugPrintf("DMA%u: Copying %u words %s 0x%08X", static_cast<u32>(channel), word_count,
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copy_to_device ? "from" : "to", current_address & mask);
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Log_DebugFmt("DMA[{}]: Copying {} words {} 0x{:08X}", channel, word_count, copy_to_device ? "from" : "to",
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current_address);
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const PhysicalMemoryAddress transfer_addr = current_address & TRANSFER_ADDRESS_MASK;
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if (CheckForBusError(channel, cs, transfer_addr, word_count * sizeof(u32))) [[unlikely]]
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return true;
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TickCount used_ticks;
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if (copy_to_device)
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used_ticks = TransferMemoryToDevice<channel>(current_address & mask, increment, word_count);
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used_ticks = TransferMemoryToDevice<channel>(transfer_addr, increment, word_count);
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else
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used_ticks = TransferDeviceToMemory<channel>(current_address & mask, increment, word_count);
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used_ticks = TransferDeviceToMemory<channel>(transfer_addr, increment, word_count);
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CPU::AddPendingTicks(used_ticks);
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CompleteTransfer(channel, cs);
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return true;
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}
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break;
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case SyncMode::LinkedList:
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{
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@ -564,43 +616,53 @@ bool DMA::TransferChannel()
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return true;
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}
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Log_DebugPrintf("DMA%u: Copying linked list starting at 0x%08X to device", static_cast<u32>(channel),
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current_address & mask);
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Log_DebugFmt("DMA[{}]: Copying linked list starting at 0x{:08X} to device", channel, current_address);
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// Prove to the compiler that nothing's going to modify these.
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const u8* const ram_ptr = Bus::g_ram;
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const u32 mask = Bus::g_ram_mask;
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u8* ram_pointer = Bus::g_ram;
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TickCount remaining_ticks = GetTransferSliceTicks();
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while (cs.request && remaining_ticks > 0)
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{
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u32 header;
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std::memcpy(&header, &ram_pointer[current_address & mask], sizeof(header));
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CPU::AddPendingTicks(10);
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remaining_ticks -= 10;
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PhysicalMemoryAddress transfer_addr = current_address & TRANSFER_ADDRESS_MASK;
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if (CheckForBusError(channel, cs, current_address, sizeof(header))) [[unlikely]]
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{
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cs.base_address = current_address;
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return true;
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}
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std::memcpy(&header, &ram_ptr[transfer_addr & mask], sizeof(header));
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const u32 word_count = header >> 24;
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const u32 next_address = header & UINT32_C(0x00FFFFFF);
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Log_TracePrintf(" .. linked list entry at 0x%08X size=%u(%u words) next=0x%08X", current_address & mask,
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word_count * UINT32_C(4), word_count, next_address);
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const u32 next_address = header & 0x00FFFFFFu;
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Log_TraceFmt(" .. linked list entry at 0x{:08X} size={}({} words) next=0x{:08X}", current_address,
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word_count * 4, word_count, next_address);
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const TickCount setup_ticks = (word_count > 0) ?
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(LINKED_LIST_HEADER_READ_TICKS + LINKED_LIST_BLOCK_SETUP_TICKS) :
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LINKED_LIST_HEADER_READ_TICKS;
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CPU::AddPendingTicks(setup_ticks);
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remaining_ticks -= setup_ticks;
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if (word_count > 0)
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{
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CPU::AddPendingTicks(5);
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remaining_ticks -= 5;
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const TickCount block_ticks =
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TransferMemoryToDevice<channel>((current_address + sizeof(header)) & mask, 4, word_count);
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const TickCount block_ticks = TransferMemoryToDevice<channel>(transfer_addr + sizeof(header), 4, word_count);
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CPU::AddPendingTicks(block_ticks);
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remaining_ticks -= block_ticks;
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}
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current_address = next_address;
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if (current_address & UINT32_C(0x800000))
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break;
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if (IsLinkedListTerminator(current_address))
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{
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// Terminator is 24 bits, so is MADR, so it'll always be 0xFFFFFF.
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cs.base_address = LINKED_LIST_TERMINATOR;
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CompleteTransfer(channel, cs);
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return true;
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}
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}
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cs.base_address = current_address;
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if (current_address & UINT32_C(0x800000))
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break;
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if (cs.request)
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{
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// stall the transfer for a bit if we ran for too long
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@ -613,7 +675,6 @@ bool DMA::TransferChannel()
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return true;
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}
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}
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break;
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case SyncMode::Request:
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{
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@ -630,30 +691,46 @@ bool DMA::TransferChannel()
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{
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do
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{
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const PhysicalMemoryAddress transfer_addr = current_address & TRANSFER_ADDRESS_MASK;
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if (CheckForBusError(channel, cs, transfer_addr, block_size * increment)) [[unlikely]]
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{
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cs.base_address = current_address;
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cs.block_control.request.block_count = blocks_remaining;
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return true;
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}
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const TickCount ticks = TransferMemoryToDevice<channel>(transfer_addr, increment, block_size);
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CPU::AddPendingTicks(ticks);
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ticks_remaining -= ticks;
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blocks_remaining--;
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const TickCount ticks = TransferMemoryToDevice<channel>(current_address & mask, increment, block_size);
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CPU::AddPendingTicks(ticks);
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ticks_remaining -= ticks;
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current_address = (current_address + (increment * block_size));
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current_address = (transfer_addr + (increment * block_size));
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} while (cs.request && blocks_remaining > 0 && ticks_remaining > 0);
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}
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else
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{
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do
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{
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const PhysicalMemoryAddress transfer_addr = current_address & TRANSFER_ADDRESS_MASK;
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if (CheckForBusError(channel, cs, transfer_addr, block_size * increment)) [[unlikely]]
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{
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cs.base_address = current_address;
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cs.block_control.request.block_count = blocks_remaining;
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return true;
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}
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const TickCount ticks = TransferDeviceToMemory<channel>(transfer_addr, increment, block_size);
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CPU::AddPendingTicks(ticks);
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ticks_remaining -= ticks;
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blocks_remaining--;
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const TickCount ticks = TransferDeviceToMemory<channel>(current_address & mask, increment, block_size);
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CPU::AddPendingTicks(ticks);
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ticks_remaining -= ticks;
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current_address = (current_address + (increment * block_size));
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current_address = (transfer_addr + (increment * block_size));
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} while (cs.request && blocks_remaining > 0 && ticks_remaining > 0);
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}
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cs.base_address = current_address & BASE_ADDRESS_MASK;
|
||||
cs.base_address = current_address;
|
||||
cs.block_control.request.block_count = blocks_remaining;
|
||||
|
||||
// finish transfer later if the request was cleared
|
||||
|
|
@ -670,25 +747,16 @@ bool DMA::TransferChannel()
|
|||
|
||||
return true;
|
||||
}
|
||||
|
||||
CompleteTransfer(channel, cs);
|
||||
return true;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
Panic("Unimplemented sync mode");
|
||||
break;
|
||||
}
|
||||
|
||||
// start/busy bit is cleared on end of transfer
|
||||
Log_DebugFmt("DMA transfer for channel {} complete", channel);
|
||||
cs.channel_control.enable_busy = false;
|
||||
if (s_DICR.IsIRQEnabled(channel))
|
||||
{
|
||||
Log_DebugFmt("Setting DMA interrupt for channel {}", channel);
|
||||
s_DICR.SetIRQFlag(channel);
|
||||
UpdateIRQ();
|
||||
}
|
||||
|
||||
return true;
|
||||
UnreachableCode();
|
||||
}
|
||||
|
||||
void DMA::HaltTransfer(TickCount duration)
|
||||
|
|
@ -726,8 +794,15 @@ void DMA::UnhaltTransfer(void*, TickCount ticks, TickCount ticks_late)
|
|||
template<DMA::Channel channel>
|
||||
TickCount DMA::TransferMemoryToDevice(u32 address, u32 increment, u32 word_count)
|
||||
{
|
||||
const u32 mask = Bus::g_ram_mask;
|
||||
#ifdef _DEBUG
|
||||
if ((address & mask) != address)
|
||||
Log_DebugFmt("DMA TO {} from masked RAM address 0x{:08X} => 0x{:08X}", channel, address, (address & mask));
|
||||
#endif
|
||||
|
||||
address &= mask;
|
||||
|
||||
const u32* src_pointer = reinterpret_cast<u32*>(Bus::g_ram + address);
|
||||
const u32 mask = GetAddressMask();
|
||||
if constexpr (channel != Channel::GPU)
|
||||
{
|
||||
if (static_cast<s32>(increment) < 0 || ((address + (increment * word_count)) & mask) <= address) [[unlikely]]
|
||||
|
|
@ -787,7 +862,14 @@ TickCount DMA::TransferMemoryToDevice(u32 address, u32 increment, u32 word_count
|
|||
template<DMA::Channel channel>
|
||||
TickCount DMA::TransferDeviceToMemory(u32 address, u32 increment, u32 word_count)
|
||||
{
|
||||
const u32 mask = GetAddressMask();
|
||||
const u32 mask = Bus::g_ram_mask;
|
||||
#ifdef _DEBUG
|
||||
if ((address & mask) != address)
|
||||
Log_DebugFmt("DMA FROM {} to masked RAM address 0x{:08X} => 0x{:08X}", channel, address, (address & mask));
|
||||
#endif
|
||||
|
||||
// TODO: This might not be correct for OTC.
|
||||
address &= mask;
|
||||
|
||||
if constexpr (channel == Channel::OTC)
|
||||
{
|
||||
|
|
@ -796,9 +878,9 @@ TickCount DMA::TransferDeviceToMemory(u32 address, u32 increment, u32 word_count
|
|||
const u32 word_count_less_1 = word_count - 1;
|
||||
for (u32 i = 0; i < word_count_less_1; i++)
|
||||
{
|
||||
u32 value = ((address - 4) & mask);
|
||||
std::memcpy(&ram_pointer[address], &value, sizeof(value));
|
||||
address = (address - 4) & mask;
|
||||
u32 next = ((address - 4) & mask);
|
||||
std::memcpy(&ram_pointer[address], &next, sizeof(next));
|
||||
address = next;
|
||||
}
|
||||
|
||||
const u32 terminator = UINT32_C(0xFFFFFF);
|
||||
|
|
@ -918,8 +1000,8 @@ void DMA::DrawDebugStateWindow()
|
|||
ImGui::TextColored(s_DPCR.GetMasterEnable(static_cast<Channel>(i)) ? active : inactive, "%u",
|
||||
s_DPCR.GetPriority(static_cast<Channel>(i)));
|
||||
ImGui::NextColumn();
|
||||
ImGui::TextColored(s_DICR.IsIRQEnabled(static_cast<Channel>(i)) ? active : inactive,
|
||||
s_DICR.IsIRQEnabled(static_cast<Channel>(i)) ? "Enabled" : "Disabled");
|
||||
ImGui::TextColored(s_DICR.GetIRQEnabled(static_cast<Channel>(i)) ? active : inactive,
|
||||
s_DICR.GetIRQEnabled(static_cast<Channel>(i)) ? "Enabled" : "Disabled");
|
||||
ImGui::NextColumn();
|
||||
ImGui::TextColored(s_DICR.GetIRQFlag(static_cast<Channel>(i)) ? active : inactive,
|
||||
s_DICR.GetIRQFlag(static_cast<Channel>(i)) ? "IRQ" : "");
|
||||
|
|
|
|||
Loading…
Reference in New Issue