Bus: Fix failed safe instruction reads raising guest exceptions
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28c88cd69f
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028a5c60d7
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@ -1015,8 +1015,8 @@ ALWAYS_INLINE static TickCount DoDMAAccess(u32 offset, u32& value)
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namespace CPU {
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template<bool add_ticks, bool icache_read = false, u32 word_count = 1>
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ALWAYS_INLINE_RELEASE void DoInstructionRead(PhysicalMemoryAddress address, void* data)
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template<bool add_ticks, bool icache_read = false, u32 word_count = 1, bool raise_exceptions>
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ALWAYS_INLINE_RELEASE bool DoInstructionRead(PhysicalMemoryAddress address, void* data)
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{
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using namespace Bus;
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@ -1027,17 +1027,24 @@ ALWAYS_INLINE_RELEASE void DoInstructionRead(PhysicalMemoryAddress address, void
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std::memcpy(data, &g_ram[address & RAM_MASK], sizeof(u32) * word_count);
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if constexpr (add_ticks)
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g_state.pending_ticks += (icache_read ? 1 : RAM_READ_TICKS) * word_count;
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return true;
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}
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else if (address >= BIOS_BASE && address < (BIOS_BASE + BIOS_SIZE))
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{
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std::memcpy(data, &g_bios[(address - BIOS_BASE) & BIOS_MASK], sizeof(u32) * word_count);
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if constexpr (add_ticks)
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g_state.pending_ticks += m_bios_access_time[static_cast<u32>(MemoryAccessSize::Word)] * word_count;
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return true;
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}
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else
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{
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if (raise_exceptions)
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CPU::RaiseException(address, Cop0Registers::CAUSE::MakeValueForException(Exception::IBE, false, false, 0));
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std::memset(data, 0, sizeof(u32) * word_count);
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return false;
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}
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}
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@ -1115,20 +1122,20 @@ u32 FillICache(VirtualMemoryAddress address)
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switch ((address >> 2) & 0x03u)
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{
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case 0:
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DoInstructionRead<true, true, 4>(address & ~(ICACHE_LINE_SIZE - 1u), line_data);
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DoInstructionRead<true, true, 4, false>(address & ~(ICACHE_LINE_SIZE - 1u), line_data);
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line_tag = GetICacheTagForAddress(address);
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break;
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case 1:
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DoInstructionRead<true, true, 3>(address & (~(ICACHE_LINE_SIZE - 1u) | 0x4), line_data + 0x4);
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DoInstructionRead<true, true, 3, false>(address & (~(ICACHE_LINE_SIZE - 1u) | 0x4), line_data + 0x4);
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line_tag = GetICacheTagForAddress(address) | 0x1;
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break;
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case 2:
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DoInstructionRead<true, true, 2>(address & (~(ICACHE_LINE_SIZE - 1u) | 0x8), line_data + 0x8);
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DoInstructionRead<true, true, 2, false>(address & (~(ICACHE_LINE_SIZE - 1u) | 0x8), line_data + 0x8);
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line_tag = GetICacheTagForAddress(address) | 0x3;
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break;
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case 3:
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default:
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DoInstructionRead<true, true, 1>(address & (~(ICACHE_LINE_SIZE - 1u) | 0xC), line_data + 0xC);
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DoInstructionRead<true, true, 1, false>(address & (~(ICACHE_LINE_SIZE - 1u) | 0xC), line_data + 0xC);
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line_tag = GetICacheTagForAddress(address) | 0x7;
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break;
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}
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@ -1402,7 +1409,7 @@ bool FetchInstruction()
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case 0x04: // KSEG0 - physical memory cached
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{
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#if 0
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DoInstructionRead<true, false, 1>(address, &g_state.next_instruction.bits);
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DoInstructionRead<true, false, 1, false>(address, &g_state.next_instruction.bits);
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#else
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if (CompareICacheTag(address))
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g_state.next_instruction.bits = ReadICache(address);
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@ -1414,7 +1421,8 @@ bool FetchInstruction()
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case 0x05: // KSEG1 - physical memory uncached
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{
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DoInstructionRead<true, false, 1>(address, &g_state.next_instruction.bits);
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if (!DoInstructionRead<true, false, 1, true>(address, &g_state.next_instruction.bits))
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return false;
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}
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break;
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@ -1443,8 +1451,7 @@ bool SafeReadInstruction(VirtualMemoryAddress addr, u32* value)
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case 0x04: // KSEG0 - physical memory cached
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case 0x05: // KSEG1 - physical memory uncached
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{
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DoInstructionRead<false, false, 1>(addr, value);
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return true;
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return DoInstructionRead<false, false, 1, false>(addr, value);
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}
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case 0x01: // KUSEG 512M-1024M
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