2019-09-17 09:22:39 +00:00
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#include "cdrom.h"
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#include "YBaseLib/Log.h"
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#include "common/state_wrapper.h"
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2019-09-17 12:18:58 +00:00
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#include "interrupt_controller.h"
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2019-09-17 09:22:39 +00:00
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Log_SetChannel(CDROM);
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CDROM::CDROM() = default;
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CDROM::~CDROM() = default;
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bool CDROM::Initialize(DMA* dma, InterruptController* interrupt_controller)
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{
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m_dma = dma;
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m_interrupt_controller = interrupt_controller;
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return true;
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}
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void CDROM::Reset()
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{
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2019-09-17 12:18:58 +00:00
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m_state = State::Idle;
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m_status.bits = 0;
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m_secondary_status.bits = 0;
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m_interrupt_enable_register = INTERRUPT_REGISTER_MASK;
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m_interrupt_flag_register = 0;
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2019-09-17 09:22:39 +00:00
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m_param_fifo.Clear();
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m_response_fifo.Clear();
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m_data_fifo.Clear();
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2019-09-17 12:18:58 +00:00
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UpdateStatusRegister();
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m_secondary_status.shell_open = true;
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2019-09-17 09:22:39 +00:00
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}
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bool CDROM::DoState(StateWrapper& sw)
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{
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sw.Do(&m_state);
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sw.Do(&m_status.bits);
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sw.Do(&m_param_fifo);
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sw.Do(&m_response_fifo);
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sw.Do(&m_data_fifo);
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return !sw.HasError();
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}
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u8 CDROM::ReadRegister(u32 offset)
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{
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switch (offset)
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{
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case 0: // status register
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return m_status.bits;
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case 1: // always response FIFO
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2019-09-17 12:18:58 +00:00
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{
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const u8 value = m_response_fifo.Pop();
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UpdateStatusRegister();
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return value;
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}
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2019-09-17 09:22:39 +00:00
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case 2: // always data FIFO
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2019-09-17 12:18:58 +00:00
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{
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const u8 value = m_data_fifo.Pop();
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UpdateStatusRegister();
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return value;
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}
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2019-09-17 09:22:39 +00:00
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case 3:
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{
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switch (m_status.index)
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{
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case 0:
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case 2:
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return m_interrupt_enable_register | ~INTERRUPT_REGISTER_MASK;
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case 1:
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case 3:
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return m_interrupt_flag_register;
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}
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}
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break;
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}
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Log_ErrorPrintf("Unknown CDROM register read: offset=0x%02X, index=%d", offset,
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ZeroExtend32(m_status.index.GetValue()));
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Panic("Unknown CDROM register");
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return 0;
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}
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void CDROM::WriteRegister(u32 offset, u8 value)
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{
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switch (offset)
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{
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case 0:
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{
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Log_DebugPrintf("CDROM status register <- 0x%02X", ZeroExtend32(value));
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m_status.bits = (m_status.bits & static_cast<u8>(~3)) | (value & u8(3));
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return;
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}
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break;
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case 1:
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{
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switch (m_status.index)
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{
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case 0:
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{
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Log_DebugPrintf("CDROM command register <- 0x%02X", ZeroExtend32(value));
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if (m_state != State::Idle)
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Log_ErrorPrintf("Ignoring write (0x%02X) to command register in non-idle state", ZeroExtend32(value));
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else
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ExecuteCommand(static_cast<Command>(value));
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return;
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}
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case 1:
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{
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Log_ErrorPrintf("Sound map data out <- 0x%02X", ZeroExtend32(value));
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return;
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}
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case 2:
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{
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Log_ErrorPrintf("Sound map coding info <- 0x%02X", ZeroExtend32(value));
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return;
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}
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case 3:
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{
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Log_ErrorPrintf("Audio volume for right-to-left output <- 0x%02X", ZeroExtend32(value));
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return;
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}
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}
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}
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break;
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case 2:
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{
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switch (m_status.index)
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{
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case 0:
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{
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if (m_param_fifo.IsFull())
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{
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Log_WarningPrintf("Parameter FIFO overflow");
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m_param_fifo.RemoveOne();
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}
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m_param_fifo.Push(value);
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2019-09-17 12:18:58 +00:00
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UpdateStatusRegister();
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2019-09-17 09:22:39 +00:00
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return;
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}
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case 1:
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{
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Log_DebugPrintf("Interrupt enable register <- 0x%02X", ZeroExtend32(value));
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m_interrupt_enable_register = value & INTERRUPT_REGISTER_MASK;
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return;
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}
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case 2:
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{
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Log_ErrorPrintf("Audio volume for left-to-left output <- 0x%02X", ZeroExtend32(value));
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return;
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}
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case 3:
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{
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Log_ErrorPrintf("Audio volume for right-to-left output <- 0x%02X", ZeroExtend32(value));
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return;
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}
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}
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}
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break;
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case 3:
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{
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switch (m_status.index)
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{
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case 0:
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{
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Log_ErrorPrintf("Request register <- 0x%02X", value);
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return;
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}
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case 1:
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{
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Log_DebugPrintf("Interrupt flag register <- 0x%02X", value);
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m_interrupt_flag_register &= ~(value & INTERRUPT_REGISTER_MASK);
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Execute();
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return;
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}
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case 2:
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{
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Log_ErrorPrintf("Audio volume for left-to-right output <- 0x%02X", ZeroExtend32(value));
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return;
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}
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case 3:
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{
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Log_ErrorPrintf("Audio volume apply changes <- 0x%02X", ZeroExtend32(value));
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return;
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}
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}
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}
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break;
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}
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Log_ErrorPrintf("Unknown CDROM register write: offset=0x%02X, index=%d, value=0x%02X", offset,
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ZeroExtend32(m_status.index.GetValue()), ZeroExtend32(value));
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}
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2019-09-17 12:18:58 +00:00
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void CDROM::SetInterrupt(Interrupt interrupt)
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{
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m_interrupt_flag_register = static_cast<u8>(interrupt);
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if (HasPendingInterrupt())
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m_interrupt_controller->InterruptRequest(InterruptController::IRQ::CDROM);
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}
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void CDROM::UpdateStatusRegister()
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{
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m_status.ADPBUSY = false;
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m_status.PRMEMPTY = m_param_fifo.IsEmpty();
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m_status.PRMWRDY = m_param_fifo.IsFull();
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m_status.RSLRRDY = !m_response_fifo.IsEmpty();
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m_status.DRQSTS = !m_data_fifo.IsEmpty();
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m_status.BUSYSTS = m_state != State::Idle;
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}
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2019-09-17 09:22:39 +00:00
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void CDROM::Execute() {}
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2019-09-17 12:18:58 +00:00
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void CDROM::ExecuteCommand(Command command)
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{
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Log_ErrorPrintf("CDROM write command 0x%02X", ZeroExtend32(static_cast<u8>(command)));
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switch (command)
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{
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case Command::Getstat:
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{
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Log_DebugPrintf("CDROM Getstat command");
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// if bit 0 or 2 is set, send an additional byte
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m_response_fifo.Push(m_secondary_status.bits);
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SetInterrupt(Interrupt::INT3);
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UpdateStatusRegister();
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}
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break;
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case Command::Test:
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{
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const u8 subcommand = m_param_fifo.Pop();
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ExecuteTestCommand(subcommand);
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}
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break;
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default:
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Panic("Unknown command");
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break;
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}
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}
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void CDROM::ExecuteTestCommand(u8 subcommand)
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{
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switch (subcommand)
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{
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case 0x20: // Get CDROM BIOS Date/Version
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{
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Log_DebugPrintf("Get CDROM BIOS Date/Version");
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static constexpr u8 response[] = {0x94, 0x09, 0x19, 0xC0};
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m_response_fifo.PushRange(response, countof(response));
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m_param_fifo.Clear();
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SetInterrupt(Interrupt::INT3);
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UpdateStatusRegister();
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return;
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}
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default:
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{
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Log_ErrorPrintf("Unknown test command 0x%02X", subcommand);
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return;
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}
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}
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2019-09-17 09:22:39 +00:00
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}
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