478 lines
12 KiB
C++
478 lines
12 KiB
C++
// Copyright (C) 2003 Dolphin Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official SVN repository and contact information can be found at
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// http://code.google.com/p/dolphin-emu/
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// http://developer.nvidia.com/object/General_FAQ.html#t6 !!!!!
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#include "Common.h"
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#include "VideoCommon.h"
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#include "ChunkFile.h"
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#include "Atomic.h"
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#include "CoreTiming.h"
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#include "ConfigManager.h"
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#include "PixelEngine.h"
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#include "CommandProcessor.h"
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#include "HW/ProcessorInterface.h"
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#include "DLCache.h"
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#include "State.h"
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namespace PixelEngine
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{
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union UPEZConfReg
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{
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u16 Hex;
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struct
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{
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u16 ZCompEnable : 1; // Z Comparator Enable
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u16 Function : 3;
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u16 ZUpdEnable : 1;
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u16 : 11;
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};
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};
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union UPEAlphaConfReg
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{
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u16 Hex;
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struct
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{
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u16 BMMath : 1; // GX_BM_BLEND || GX_BM_SUBSTRACT
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u16 BMLogic : 1; // GX_BM_LOGIC
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u16 Dither : 1;
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u16 ColorUpdEnable : 1;
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u16 AlphaUpdEnable : 1;
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u16 DstFactor : 3;
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u16 SrcFactor : 3;
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u16 Substract : 1; // Additive mode by default
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u16 BlendOperator : 4;
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};
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};
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union UPEDstAlphaConfReg
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{
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u16 Hex;
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struct
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{
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u16 DstAlpha : 8;
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u16 Enable : 1;
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u16 : 7;
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};
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};
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union UPEAlphaModeConfReg
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{
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u16 Hex;
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struct
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{
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u16 Threshold : 8;
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u16 CompareMode : 8;
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};
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};
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// fifo Control Register
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union UPECtrlReg
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{
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struct
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{
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u16 PETokenEnable : 1;
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u16 PEFinishEnable : 1;
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u16 PEToken : 1; // write only
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u16 PEFinish : 1; // write only
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u16 : 12;
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};
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u16 Hex;
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UPECtrlReg() {Hex = 0; }
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UPECtrlReg(u16 _hex) {Hex = _hex; }
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};
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// STATE_TO_SAVE
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static UPEZConfReg m_ZConf;
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static UPEAlphaConfReg m_AlphaConf;
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static UPEDstAlphaConfReg m_DstAlphaConf;
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static UPEAlphaModeConfReg m_AlphaModeConf;
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static UPEAlphaReadReg m_AlphaRead;
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static UPECtrlReg m_Control;
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//static u16 m_Token; // token value most recently encountered
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static bool g_bSignalTokenInterrupt;
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static bool g_bSignalFinishInterrupt;
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static int et_SetTokenOnMainThread;
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static int et_SetFinishOnMainThread;
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volatile bool interruptSetToken = false;
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volatile bool interruptSetFinish = false;
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u16 bbox[4];
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bool bbox_active;
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enum
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{
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INT_CAUSE_PE_TOKEN = 0x200, // GP Token
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INT_CAUSE_PE_FINISH = 0x400, // GP Finished
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};
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void DoState(PointerWrap &p)
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{
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p.Do(m_ZConf);
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p.Do(m_AlphaConf);
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p.Do(m_DstAlphaConf);
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p.Do(m_AlphaModeConf);
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p.Do(m_AlphaRead);
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p.Do(m_Control);
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p.Do(g_bSignalTokenInterrupt);
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p.Do(g_bSignalFinishInterrupt);
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p.Do(interruptSetToken);
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p.Do(interruptSetFinish);
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p.Do(bbox);
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p.Do(bbox_active);
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}
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void UpdateInterrupts();
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void UpdateTokenInterrupt(bool active);
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void UpdateFinishInterrupt(bool active);
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void SetToken_OnMainThread(u64 userdata, int cyclesLate);
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void SetFinish_OnMainThread(u64 userdata, int cyclesLate);
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void Init()
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{
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m_Control.Hex = 0;
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m_ZConf.Hex = 0;
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m_AlphaConf.Hex = 0;
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m_DstAlphaConf.Hex = 0;
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m_AlphaModeConf.Hex = 0;
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m_AlphaRead.Hex = 0;
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g_bSignalTokenInterrupt = false;
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g_bSignalFinishInterrupt = false;
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interruptSetToken = false;
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interruptSetFinish = false;
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et_SetTokenOnMainThread = CoreTiming::RegisterEvent("SetToken", SetToken_OnMainThread);
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et_SetFinishOnMainThread = CoreTiming::RegisterEvent("SetFinish", SetFinish_OnMainThread);
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bbox[0] = 0x80;
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bbox[1] = 0xA0;
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bbox[2] = 0x80;
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bbox[3] = 0xA0;
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bbox_active = false;
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}
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void Read16(u16& _uReturnValue, const u32 _iAddress)
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{
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DEBUG_LOG(PIXELENGINE, "(r16) 0x%08x", _iAddress);
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switch (_iAddress & 0xFFF)
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{
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// CPU Direct Access EFB Raster State Config
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case PE_ZCONF:
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_uReturnValue = m_ZConf.Hex;
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INFO_LOG(PIXELENGINE, "(r16) ZCONF");
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break;
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case PE_ALPHACONF:
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// Most games read this early. no idea why.
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_uReturnValue = m_AlphaConf.Hex;
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INFO_LOG(PIXELENGINE, "(r16) ALPHACONF");
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break;
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case PE_DSTALPHACONF:
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_uReturnValue = m_DstAlphaConf.Hex;
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INFO_LOG(PIXELENGINE, "(r16) DSTALPHACONF");
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break;
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case PE_ALPHAMODE:
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_uReturnValue = m_AlphaModeConf.Hex;
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INFO_LOG(PIXELENGINE, "(r16) ALPHAMODE");
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break;
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case PE_ALPHAREAD:
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_uReturnValue = m_AlphaRead.Hex;
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WARN_LOG(PIXELENGINE, "(r16) ALPHAREAD");
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break;
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case PE_CTRL_REGISTER:
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_uReturnValue = m_Control.Hex;
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INFO_LOG(PIXELENGINE, "(r16) CTRL_REGISTER : %04x", _uReturnValue);
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break;
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case PE_TOKEN_REG:
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_uReturnValue = CommandProcessor::fifo.PEToken;
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INFO_LOG(PIXELENGINE, "(r16) TOKEN_REG : %04x", _uReturnValue);
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break;
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case PE_BBOX_LEFT:
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{
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// Left must be even and 606px max
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_uReturnValue = std::min((u16) 606, bbox[0]) & ~1;
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INFO_LOG(PIXELENGINE, "R: BBOX_LEFT = %i", _uReturnValue);
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bbox_active = false;
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break;
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}
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case PE_BBOX_RIGHT:
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{
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// Right must be odd and 607px max
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_uReturnValue = std::min((u16) 607, bbox[1]) | 1;
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INFO_LOG(PIXELENGINE, "R: BBOX_RIGHT = %i", _uReturnValue);
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bbox_active = false;
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break;
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}
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case PE_BBOX_TOP:
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{
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// Top must be even and 478px max
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_uReturnValue = std::min((u16) 478, bbox[2]) & ~1;
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INFO_LOG(PIXELENGINE, "R: BBOX_TOP = %i", _uReturnValue);
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bbox_active = false;
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break;
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}
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case PE_BBOX_BOTTOM:
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{
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// Bottom must be odd and 479px max
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_uReturnValue = std::min((u16) 479, bbox[3]) | 1;
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INFO_LOG(PIXELENGINE, "R: BBOX_BOTTOM = %i", _uReturnValue);
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bbox_active = false;
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break;
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}
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case PE_PERF_0L:
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case PE_PERF_0H:
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case PE_PERF_1L:
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case PE_PERF_1H:
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case PE_PERF_2L:
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case PE_PERF_2H:
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case PE_PERF_3L:
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case PE_PERF_3H:
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case PE_PERF_4L:
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case PE_PERF_4H:
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case PE_PERF_5L:
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case PE_PERF_5H:
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INFO_LOG(PIXELENGINE, "(r16) perf counter @ %08x", _iAddress);
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// git r90a2096a24f4 (svn r3663) added the PE_PERF cases, without setting
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// _uReturnValue to anything, this reverts to the previous behaviour which allows
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// The timer in SMS:Scrubbing Serena Beach to countdown correctly
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_uReturnValue = 1;
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break;
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default:
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INFO_LOG(PIXELENGINE, "(r16) unknown @ %08x", _iAddress);
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_uReturnValue = 1;
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break;
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}
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}
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void Write16(const u16 _iValue, const u32 _iAddress)
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{
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switch (_iAddress & 0xFFF)
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{
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// CPU Direct Access EFB Raster State Config
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case PE_ZCONF:
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m_ZConf.Hex = _iValue;
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INFO_LOG(PIXELENGINE, "(w16) ZCONF: %02x", _iValue);
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break;
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case PE_ALPHACONF:
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m_AlphaConf.Hex = _iValue;
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INFO_LOG(PIXELENGINE, "(w16) ALPHACONF: %02x", _iValue);
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break;
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case PE_DSTALPHACONF:
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m_DstAlphaConf.Hex = _iValue;
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INFO_LOG(PIXELENGINE, "(w16) DSTALPHACONF: %02x", _iValue);
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break;
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case PE_ALPHAMODE:
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m_AlphaModeConf.Hex = _iValue;
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INFO_LOG(PIXELENGINE, "(w16) ALPHAMODE: %02x", _iValue);
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break;
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case PE_ALPHAREAD:
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m_AlphaRead.Hex = _iValue;
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INFO_LOG(PIXELENGINE, "(w16) ALPHAREAD: %02x", _iValue);
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break;
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case PE_CTRL_REGISTER:
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{
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UPECtrlReg tmpCtrl(_iValue);
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if (tmpCtrl.PEToken) g_bSignalTokenInterrupt = false;
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if (tmpCtrl.PEFinish) g_bSignalFinishInterrupt = false;
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m_Control.PETokenEnable = tmpCtrl.PETokenEnable;
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m_Control.PEFinishEnable = tmpCtrl.PEFinishEnable;
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m_Control.PEToken = 0; // this flag is write only
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m_Control.PEFinish = 0; // this flag is write only
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DEBUG_LOG(PIXELENGINE, "(w16) CTRL_REGISTER: 0x%04x", _iValue);
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UpdateInterrupts();
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}
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break;
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case PE_TOKEN_REG:
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PanicAlert("(w16) WTF? PowerPC program wrote token: %i", _iValue);
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//only the gx pipeline is supposed to be able to write here
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//g_token = _iValue;
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break;
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default:
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WARN_LOG(PIXELENGINE, "(w16) unknown %04x @ %08x", _iValue, _iAddress);
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break;
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}
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}
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void Write32(const u32 _iValue, const u32 _iAddress)
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{
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WARN_LOG(PIXELENGINE, "(w32) 0x%08x @ 0x%08x IGNORING...",_iValue,_iAddress);
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}
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bool AllowIdleSkipping()
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{
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return !SConfig::GetInstance().m_LocalCoreStartupParameter.bCPUThread || (!m_Control.PETokenEnable && !m_Control.PEFinishEnable);
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}
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void UpdateInterrupts()
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{
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// check if there is a token-interrupt
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UpdateTokenInterrupt((g_bSignalTokenInterrupt & m_Control.PETokenEnable));
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// check if there is a finish-interrupt
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UpdateFinishInterrupt((g_bSignalFinishInterrupt & m_Control.PEFinishEnable));
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}
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void UpdateTokenInterrupt(bool active)
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{
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ProcessorInterface::SetInterrupt(INT_CAUSE_PE_TOKEN, active);
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interruptSetToken = active;
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}
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void UpdateFinishInterrupt(bool active)
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{
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ProcessorInterface::SetInterrupt(INT_CAUSE_PE_FINISH, active);
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interruptSetFinish = active;
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}
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// TODO(mb2): Refactor SetTokenINT_OnMainThread(u64 userdata, int cyclesLate).
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// Think about the right order between tokenVal and tokenINT... one day maybe.
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// Cleanup++
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// Called only if BPMEM_PE_TOKEN_INT_ID is ack by GP
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void SetToken_OnMainThread(u64 userdata, int cyclesLate)
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{
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//if (userdata >> 16)
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//{
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g_bSignalTokenInterrupt = true;
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//_dbg_assert_msg_(PIXELENGINE, (CommandProcessor::fifo.PEToken == (userdata&0xFFFF)), "WTF? BPMEM_PE_TOKEN_INT_ID's token != BPMEM_PE_TOKEN_ID's token" );
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INFO_LOG(PIXELENGINE, "VIDEO Backend raises INT_CAUSE_PE_TOKEN (btw, token: %04x)", CommandProcessor::fifo.PEToken);
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UpdateInterrupts();
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CommandProcessor::interruptTokenWaiting = false;
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IncrementCheckContextId();
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//}
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}
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void SetFinish_OnMainThread(u64 userdata, int cyclesLate)
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{
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g_bSignalFinishInterrupt = 1;
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UpdateInterrupts();
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CommandProcessor::interruptFinishWaiting = false;
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CommandProcessor::isPossibleWaitingSetDrawDone = false;
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}
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// SetToken
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// THIS IS EXECUTED FROM VIDEO THREAD
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void SetToken(const u16 _token, const int _bSetTokenAcknowledge)
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{
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// TODO?: set-token-value and set-token-INT could be merged since set-token-INT own the token value.
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if (_bSetTokenAcknowledge) // set token INT
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{
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Common::AtomicStore(*(volatile u32*)&CommandProcessor::fifo.PEToken, _token);
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CommandProcessor::interruptTokenWaiting = true;
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CoreTiming::ScheduleEvent_Threadsafe(0, et_SetTokenOnMainThread, _token | (_bSetTokenAcknowledge << 16));
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}
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else // set token value
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{
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// we do it directly from videoThread because of
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// Super Monkey Ball
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// XXX: No 16-bit atomic store available, so cheat and use 32-bit.
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// That's what we've always done. We're counting on fifo.PEToken to be
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// 4-byte padded.
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Common::AtomicStore(*(volatile u32*)&CommandProcessor::fifo.PEToken, _token);
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}
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IncrementCheckContextId();
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}
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// SetFinish
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// THIS IS EXECUTED FROM VIDEO THREAD (BPStructs.cpp) when a new frame has been drawn
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void SetFinish()
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{
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CommandProcessor::interruptFinishWaiting = true;
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CoreTiming::ScheduleEvent_Threadsafe(0, et_SetFinishOnMainThread, 0);
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INFO_LOG(PIXELENGINE, "VIDEO Set Finish");
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IncrementCheckContextId();
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}
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//This function is used in CommandProcessor when write CTRL_REGISTER and the new fifo is attached.
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void ResetSetFinish()
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{
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//if SetFinish happened but PE_CTRL_REGISTER not, I reset the interrupt else
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//remove event from the queque
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if (g_bSignalFinishInterrupt)
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{
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UpdateFinishInterrupt(false);
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g_bSignalFinishInterrupt = false;
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}
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else
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{
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CoreTiming::RemoveEvent(et_SetFinishOnMainThread);
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}
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CommandProcessor::interruptFinishWaiting = false;
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}
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void ResetSetToken()
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{
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if (g_bSignalTokenInterrupt)
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{
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UpdateTokenInterrupt(false);
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g_bSignalTokenInterrupt = false;
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}
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else
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{
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CoreTiming::RemoveEvent(et_SetTokenOnMainThread);
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}
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CommandProcessor::interruptTokenWaiting = false;
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}
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bool WaitingForPEInterrupt()
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{
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return !CommandProcessor::waitingForPEInterruptDisable && (CommandProcessor::interruptFinishWaiting || CommandProcessor::interruptTokenWaiting || interruptSetFinish || interruptSetToken);
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}
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void ResumeWaitingForPEInterrupt()
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{
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interruptSetFinish = false;
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interruptSetToken = false;
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CommandProcessor::interruptFinishWaiting = false;
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CommandProcessor::interruptTokenWaiting = false;
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}
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} // end of namespace PixelEngine
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