156 lines
4.3 KiB
C++
156 lines
4.3 KiB
C++
// stdafx.cpp : source file that includes just the standard includes
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// DSP_InterC.pch will be the pre-compiled header
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// stdafx.obj will contain the pre-compiled type information
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#include "stdafx.h"
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#include <stdarg.h>
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#include <stdio.h>
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namespace OutBuffer
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{
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void Init()
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{
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}
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void Add(const char* _fmt, ...)
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{
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static char Msg[2048];
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va_list ap;
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va_start(ap, _fmt);
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vsprintf(Msg, _fmt, ap);
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va_end(ap);
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printf("%s\n", Msg);
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}
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void AddCode(const char* _fmt, ...)
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{
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static char Msg[2048];
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va_list ap;
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va_start(ap, _fmt);
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vsprintf(Msg, _fmt, ap);
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va_end(ap);
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printf(" %s;\n", Msg);
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}
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// predefined labels
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typedef struct pdlabel_t
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{
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uint16 addr;
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const char* name;
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const char* description;
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} pdlabels_t;
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pdlabel_t regnames[] =
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{
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{0x00, "R00", "Register 00",},
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{0x01, "R01", "Register 01",},
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{0x02, "R02", "Register 02",},
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{0x03, "R03", "Register 03",},
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{0x04, "R04", "Register 04",},
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{0x05, "R05", "Register 05",},
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{0x06, "R06", "Register 06",},
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{0x07, "R07", "Register 07",},
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{0x08, "R08", "Register 08",},
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{0x09, "R09", "Register 09",},
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{0x0a, "R10", "Register 10",},
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{0x0b, "R11", "Register 11",},
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{0x0c, "ST0", "Call stack",},
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{0x0d, "ST1", "Data stack",},
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{0x0e, "ST2", "Loop address stack",},
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{0x0f, "ST3", "Loop counter",},
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{0x00, "ACH0", "Accumulator High 0",},
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{0x11, "ACH1", "Accumulator High 1",},
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{0x12, "CR", "Config Register",},
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{0x13, "SR", "Special Register",},
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{0x14, "PROD_l", "PROD L",},
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{0x15, "PROD_m1", "PROD M1",},
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{0x16, "PROD_h", "PROD H",},
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{0x17, "PROD_m2", "PROD M2",},
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{0x18, "AX0_l", "Additional Accumulators Low 0",},
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{0x19, "AX1_l", "Additional Accumulators Low 1",},
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{0x1a, "AX0_h", "Additional Accumulators High 0",},
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{0x1b, "AX1_h", "Additional Accumulators High 1",},
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{0x1c, "AC0_l", "Register 28",},
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{0x1d, "AC1_l", "Register 29",},
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{0x1e, "AC0_m", "Register 00",},
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{0x1f, "AC1_m", "Register 00",},
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// additional to resolve special names
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{0x20, "ACC0", "Accumulators 0",},
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{0x21, "ACC1", "Accumulators 1",},
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{0x22, "AX0", "Additional Accumulators 0",},
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{0x23, "AX1", "Additional Accumulators 1",},
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};
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const pdlabel_t pdlabels[] =
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{
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{0xffa0, "COEF_A1_0", "COEF_A1_0",},
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{0xffa1, "COEF_A2_0", "COEF_A2_0",},
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{0xffa2, "COEF_A1_1", "COEF_A1_1",},
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{0xffa3, "COEF_A2_1", "COEF_A2_1",},
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{0xffa4, "COEF_A1_2", "COEF_A1_2",},
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{0xffa5, "COEF_A2_2", "COEF_A2_2",},
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{0xffa6, "COEF_A1_3", "COEF_A1_3",},
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{0xffa7, "COEF_A2_3", "COEF_A2_3",},
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{0xffa8, "COEF_A1_4", "COEF_A1_4",},
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{0xffa9, "COEF_A2_4", "COEF_A2_4",},
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{0xffaa, "COEF_A1_5", "COEF_A1_5",},
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{0xffab, "COEF_A2_5", "COEF_A2_5",},
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{0xffac, "COEF_A1_6", "COEF_A1_6",},
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{0xffad, "COEF_A2_6", "COEF_A2_6",},
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{0xffae, "COEF_A1_7", "COEF_A1_7",},
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{0xffaf, "COEF_A2_7", "COEF_A2_7",},
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{0xffc9, "DSCR", "DSP DMA Control Reg",},
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{0xffcb, "DSBL", "DSP DMA Block Length",},
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{0xffcd, "DSPA", "DSP DMA DMEM Address",},
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{0xffce, "DSMAH", "DSP DMA Mem Address H",},
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{0xffcf, "DSMAL", "DSP DMA Mem Address L",},
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{0xffd1, "SampleFormat", "SampleFormat",},
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{0xffd3, "Unk Zelda", "Unk Zelda writes to it",},
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{0xffd4, "ACSAH", "Accelerator start address H",},
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{0xffd5, "ACSAL", "Accelerator start address L",},
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{0xffd6, "ACEAH", "Accelerator end address H",},
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{0xffd7, "ACEAL", "Accelerator end address L",},
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{0xffd8, "ACCAH", "Accelerator current address H",},
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{0xffd9, "ACCAL", "Accelerator current address L",},
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{0xffda, "pred_scale", "pred_scale",},
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{0xffdb, "yn1", "yn1",},
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{0xffdc, "yn2", "yn2",},
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{0xffdd, "ARAM", "Direct Read from ARAM (uses ADPCM)",},
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{0xffde, "GAIN", "Gain",},
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{0xffef, "AMDM", "ARAM DMA Request Mask",},
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{0xfffb, "DIRQ", "DSP IRQ Request",},
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{0xfffc, "DMBH", "DSP Mailbox H",},
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{0xfffd, "DMBL", "DSP Mailbox L",},
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{0xfffe, "CMBH", "CPU Mailbox H",},
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{0xffff, "CMBL", "CPU Mailbox L",},
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};
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const char* GetRegName(uint16 reg)
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{
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return regnames[reg].name;
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}
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const char* GetMemName(uint16 addr)
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{
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static char Buffer[1024];
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for (int i=0; i<sizeof(pdlabels); i++)
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{
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if (pdlabels[i].addr == addr)
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return pdlabels[i].name;
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}
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sprintf(Buffer, "0x%4x", addr);
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return Buffer;
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}
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}
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