190 lines
4.8 KiB
C++
190 lines
4.8 KiB
C++
// Copyright (C) 2003 Dolphin Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official SVN repository and contact information can be found at
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// http://code.google.com/p/dolphin-emu/
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// Additional copyrights go to Duddie and Tratax (c) 2004
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#include "DSPInterpreter.h"
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#include "DSPCore.h"
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#include "DSPIntUtil.h"
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namespace DSPInterpreter {
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// MRR $D, $S
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// 0001 11dd ddds ssss
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// Move value from register $S to register $D.
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// FIXME: Perform additional operation depending on destination register.
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void mrr(const UDSPInstruction opc)
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{
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u8 sreg = opc & 0x1f;
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u8 dreg = (opc >> 5) & 0x1f;
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u16 val = dsp_op_read_reg(sreg);
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dsp_op_write_reg(dreg, val);
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dsp_conditional_extend_accum(dreg);
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}
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// LRI $D, #I
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// 0000 0000 100d dddd
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// iiii iiii iiii iiii
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// Load immediate value I to register $D.
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//
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// DSPSpy discovery: This, and possibly other instructions that load a
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// register, has a different behaviour in S40 mode if loaded to AC0.M: The
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// value gets sign extended to the whole accumulator! This does not happen in
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// S16 mode.
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void lri(const UDSPInstruction opc)
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{
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u8 reg = opc & DSP_REG_MASK;
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u16 imm = dsp_fetch_code();
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dsp_op_write_reg(reg, imm);
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dsp_conditional_extend_accum(reg);
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}
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// LRIS $(0x18+D), #I
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// 0000 1ddd iiii iiii
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// Load immediate value I (8-bit sign extended) to accumulator register.
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void lris(const UDSPInstruction opc)
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{
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u8 reg = ((opc >> 8) & 0x7) + DSP_REG_AXL0;
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u16 imm = (s8)opc;
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dsp_op_write_reg(reg, imm);
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dsp_conditional_extend_accum(reg);
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}
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//----
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// NX
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// 1000 -000 xxxx xxxx
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// No operation, but can be extended with extended opcode.
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// This opcode is supposed to do nothing - it's used if you want to use
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// an opcode extension but not do anything. At least according to duddie.
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void nx(const UDSPInstruction opc)
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{
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zeroWriteBackLog();
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}
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//----
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// DAR $arD
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// 0000 0000 0000 01dd
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// Decrement address register $arD.
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void dar(const UDSPInstruction opc)
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{
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g_dsp.r[opc & 0x3] = dsp_decrement_addr_reg(opc & 0x3);
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}
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// IAR $arD
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// 0000 0000 0000 10dd
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// Increment address register $arD.
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void iar(const UDSPInstruction opc)
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{
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g_dsp.r[opc & 0x3] = dsp_increment_addr_reg(opc & 0x3);
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}
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// SUBARN $arD
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// 0000 0000 0000 11dd
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// Subtract indexing register $ixD from an addressing register $arD.
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// used only in IPL-NTSC ucode
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void subarn(const UDSPInstruction opc)
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{
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u8 dreg = opc & 0x3;
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g_dsp.r[dreg] = dsp_decrease_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + dreg]);
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}
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// ADDARN $arD, $ixS
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// 0000 0000 0001 ssdd
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// Adds indexing register $ixS to an addressing register $arD.
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// It is critical for the Zelda ucode that this one wraps correctly.
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void addarn(const UDSPInstruction opc)
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{
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u8 dreg = opc & 0x3;
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u8 sreg = (opc >> 2) & 0x3;
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g_dsp.r[dreg] = dsp_increase_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
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}
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//----
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// SBCLR #I
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// 0001 0011 aaaa aiii
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// bit of status register $sr. Bit number is calculated by adding 6 to
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// immediate value I.
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void sbclr(const UDSPInstruction opc)
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{
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u8 bit = (opc & 0x7) + 6;
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g_dsp.r[DSP_REG_SR] &= ~(1 << bit);
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}
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// SBSET #I
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// 0001 0010 aaaa aiii
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// Set bit of status register $sr. Bit number is calculated by adding 6 to
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// immediate value I.
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void sbset(const UDSPInstruction opc)
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{
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u8 bit = (opc & 0x7) + 6;
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g_dsp.r[DSP_REG_SR] |= (1 << bit);
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}
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// This is a bunch of flag setters, flipping bits in SR. So far so good,
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// but it's harder to know exactly what effect they have.
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void srbith(const UDSPInstruction opc)
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{
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zeroWriteBackLog();
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switch ((opc >> 8) & 0xf)
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{
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// M0/M2 change the multiplier mode (it can multiply by 2 for free).
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case 0xa: // M2
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g_dsp.r[DSP_REG_SR] &= ~SR_MUL_MODIFY;
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break;
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case 0xb: // M0
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g_dsp.r[DSP_REG_SR] |= SR_MUL_MODIFY;
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break;
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// If set, treat multiplicands as unsigned.
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// If clear, treat them as signed.
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case 0xc: // CLR15
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g_dsp.r[DSP_REG_SR] &= ~SR_MUL_UNSIGNED;
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break;
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case 0xd: // SET15
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g_dsp.r[DSP_REG_SR] |= SR_MUL_UNSIGNED;
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break;
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// Automatic 40-bit sign extension when loading ACx.M.
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// SET40 changes something very important: see the LRI instruction above.
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case 0xe: // SET16 (CLR40)
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g_dsp.r[DSP_REG_SR] &= ~SR_40_MODE_BIT;
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break;
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case 0xf: // SET40
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g_dsp.r[DSP_REG_SR] |= SR_40_MODE_BIT;
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break;
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default:
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break;
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}
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}
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//----
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void unknown(const UDSPInstruction opc)
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{
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ERROR_LOG(DSPLLE, "LLE: Unrecognized opcode 0x%04x, pc 0x%04x", opc, g_dsp.pc);
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}
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} // namespace
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