488 lines
13 KiB
C++
488 lines
13 KiB
C++
/*====================================================================
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filename: opcodes.h
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project: GameCube DSP Tool (gcdsp)
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created: 2005.03.04
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mail: duddie@walla.com
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Copyright (c) 2005 Duddie
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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====================================================================*/
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#include "DSPIntUtil.h"
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#include "DSPMemoryMap.h"
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#include "DSPIntExtOps.h"
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// Extended opcodes do not exist on their own. These opcodes can only be
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// attached to opcodes that allow extending (8 lower bits of opcode not used by
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// opcode). Extended opcodes do not modify program counter $pc register.
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// Most of the suffixes increment or decrement one or more addressing registers
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// (the first four, ARx). The increment/decrement is either 1, or the corresponding
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// "index" register (the second four, IXx). The addressing registers will wrap
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// in odd ways, dictated by the corresponding wrapping register, WP0-3.
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// The following should be applied as a decrement (and is applied by dsp_decrement_addr_reg):
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// ar[i] = (ar[i] & wp[i]) == 0 ? ar[i] | wp[i] : ar[i] - 1;
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// I have not found the corresponding algorithms for increments yet.
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// It's gotta be fairly simple though. See R3123, R3125 in Google Code.
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// (May have something to do with (ar[i] ^ wp[i]) == 0)
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namespace DSPInterpreter
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{
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namespace Ext
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{
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u16 cache1;
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// DR $arR
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// xxxx xxxx 0000 01rr
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// Decrement addressing register $arR.
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void dr(const UDSPInstruction& opc) {
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dsp_decrement_addr_reg(opc.hex & 0x3);
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}
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// IR $arR
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// xxxx xxxx 0000 10rr
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// Increment addressing register $arR.
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void ir(const UDSPInstruction& opc) {
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dsp_increment_addr_reg(opc.hex & 0x3);
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}
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// NR $arR
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// xxxx xxxx 0000 11rr
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// Add corresponding indexing register $ixR to addressing register $arR.
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void nr(const UDSPInstruction& opc) {
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u8 reg = opc.hex & 0x3;
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dsp_increase_addr_reg(reg, (s16)g_dsp.r[DSP_REG_IX0 + reg]);
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}
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// MV $axD, $acS.l
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// xxxx xxxx 0001 ddss
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// Move value of $acS.l to the $axD.l.
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void mv(const UDSPInstruction& opc)
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{
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u8 sreg = opc.hex & 0x3;
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cache1 = g_dsp.r[sreg + DSP_REG_ACC0];
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currentEpilogeFunc = mv_epi;
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}
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void mv_epi(const UDSPInstruction& opc)
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{
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u8 dreg = ((opc.hex >> 2) & 0x3);
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g_dsp.r[dreg + DSP_REG_AXL0] = cache1;
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}
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// S @$D, $acD.l
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// xxxx xxxx 001s s0dd
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// Store value of $(acS.l) in the memory pointed by register $D.
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// Post increment register $D.
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void s(const UDSPInstruction& opc)
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{
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u8 dreg = opc.hex & 0x3;
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u8 sreg = ((opc.hex >> 3) & 0x3) + DSP_REG_ACC0;
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dsp_dmem_write(g_dsp.r[dreg], g_dsp.r[sreg]);
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currentEpilogeFunc = s_epi;
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}
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void s_epi(const UDSPInstruction& opc)
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{
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u8 dreg = opc.hex & 0x3;
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dsp_increment_addr_reg(dreg);
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}
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// SN @$D, $acD.l
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// xxxx xxxx 001s s1dd
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// Store value of register $acS in the memory pointed by register $D.
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// Add indexing register $ixD to register $D.
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void sn(const UDSPInstruction& opc)
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{
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u8 dreg = opc.hex & 0x3;
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u8 sreg = ((opc.hex >> 3) & 0x3) + DSP_REG_ACC0;
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dsp_dmem_write(g_dsp.r[dreg], g_dsp.r[sreg]);
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currentEpilogeFunc = sn_epi;
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}
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void sn_epi(const UDSPInstruction& opc)
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{
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u8 dreg = opc.hex & 0x3;
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dsp_increase_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + dreg]);
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}
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// L axD.l, @$S
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// xxxx xxxx 01dd d0ss
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// Load $axD with value from memory pointed by register $S.
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// Post increment register $S.
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void l(const UDSPInstruction& opc)
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{
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u8 sreg = opc.hex & 0x3;
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cache1 = dsp_dmem_read(g_dsp.r[sreg]);
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currentEpilogeFunc = l_epi;
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}
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void l_epi(const UDSPInstruction& opc) {
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u8 sreg = opc.hex & 0x3;
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u8 dreg = ((opc.hex >> 3) & 0x7) + DSP_REG_AXL0;
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g_dsp.r[dreg] = cache1;
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dsp_increment_addr_reg(sreg);
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}
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// LN axD.l, @$S
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// xxxx xxxx 01dd d0ss
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// Load $axD with value from memory pointed by register $S.
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// Add indexing register register $ixS to register $S.
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void ln(const UDSPInstruction& opc)
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{
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u8 sreg = opc.hex & 0x3;
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u8 dreg = ((opc.hex >> 3) & 0x7) + DSP_REG_AXL0;
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cache1 = dsp_dmem_read(g_dsp.r[sreg]);
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currentEpilogeFunc = ln_epi;
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}
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void ln_epi(const UDSPInstruction& opc)
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{
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u8 sreg = opc.hex & 0x3;
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u8 dreg = ((opc.hex >> 3) & 0x7) + DSP_REG_AXL0;
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g_dsp.r[dreg] = cache1;
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dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
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}
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// LS $axD.l, $acS.m
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// xxxx xxxx 10dd 000s
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// Load register $axD.l with value from memory pointed by register
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// $ar0. Store value from register $acS.m to memory location pointed by
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// register $ar3. Increment both $ar0 and $ar3.
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void ls(const UDSPInstruction& opc)
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{
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u8 areg = (opc.hex & 0x1) + DSP_REG_ACM0;
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u8 sreg = 0x03;
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dsp_dmem_write(g_dsp.r[sreg], g_dsp.r[areg]);
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dsp_increment_addr_reg(sreg);
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currentEpilogeFunc = ls_epi;
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}
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void ls_epi(const UDSPInstruction& opc)
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{
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u8 dreg = ((opc.hex >> 4) & 0x3) + DSP_REG_AXL0;
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u16 val = dsp_dmem_read(g_dsp.r[0x00]);
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dsp_op_write_reg(dreg, val);
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dsp_increment_addr_reg(0x00);
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}
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// LSN $acD.l, $acS.m
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// xxxx xxxx 10dd 010s
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// Load register $acD.l with value from memory pointed by register
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// $ar0. Store value from register $acS.m to memory location pointed by
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// register $ar3. Add corresponding indexing register $ix0 to addressing
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// register $ar0 and increment $ar3.
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void lsn(const UDSPInstruction& opc)
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{
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u8 areg = (opc.hex & 0x1) + DSP_REG_ACM0;
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u8 sreg = 0x03;
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dsp_dmem_write(g_dsp.r[sreg], g_dsp.r[areg]);
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dsp_increment_addr_reg(sreg);
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currentEpilogeFunc = lsn_epi;
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}
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void lsn_epi(const UDSPInstruction& opc)
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{
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u8 dreg = ((opc.hex >> 4) & 0x3) + DSP_REG_AXL0;
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u16 val = dsp_dmem_read(g_dsp.r[0x00]);
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dsp_op_write_reg(dreg, val);
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dsp_increase_addr_reg(0x00, (s16)g_dsp.r[DSP_REG_IX0]);
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}
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// LSM $acD.l, $acS.m
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// xxxx xxxx 10dd 100s
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// Load register $acD.l with value from memory pointed by register
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// $ar0. Store value from register $acS.m to memory location pointed by
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// register $ar3. Add corresponding indexing register $ix3 to addressing
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// register $ar3 and increment $ar0.
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void lsm(const UDSPInstruction& opc)
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{
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u8 areg = (opc.hex & 0x1) + DSP_REG_ACM0;
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u8 sreg = 0x03;
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dsp_dmem_write(g_dsp.r[sreg], g_dsp.r[areg]);
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dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
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currentEpilogeFunc = lsm_epi;
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}
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void lsm_epi(const UDSPInstruction& opc)
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{
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u8 dreg = ((opc.hex >> 4) & 0x3) + DSP_REG_AXL0;
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u16 val = dsp_dmem_read(g_dsp.r[0x00]);
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dsp_op_write_reg(dreg, val);
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dsp_increment_addr_reg(0x00);
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}
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// LSMN $acD.l, $acS.m
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// xxxx xxxx 10dd 110s
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// Load register $acD.l with value from memory pointed by register
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// $ar0. Store value from register $acS.m to memory location pointed by
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// register $ar3. Add corresponding indexing register $ix0 to addressing
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// register $ar0 and add corresponding indexing register $ix3 to addressing
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// register $ar3.
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void lsnm(const UDSPInstruction& opc)
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{
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u8 areg = (opc.hex & 0x1) + DSP_REG_ACM0;
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u8 sreg = 0x03;
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dsp_dmem_write(g_dsp.r[sreg], g_dsp.r[areg]);
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dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
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currentEpilogeFunc = lsnm_epi;
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}
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void lsnm_epi(const UDSPInstruction& opc)
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{
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u8 dreg = ((opc.hex >> 4) & 0x3) + DSP_REG_AXL0;
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u16 val = dsp_dmem_read(g_dsp.r[0x00]);
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dsp_op_write_reg(dreg, val);
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dsp_increase_addr_reg(0x00, (s16)g_dsp.r[DSP_REG_IX0]);
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}
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// SL $acS.m, $acD.l
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// xxxx xxxx 10dd 001s
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// Store value from register $acS.m to memory location pointed by register
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// $ar0. Load register $acD.l with value from memory pointed by register
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// $ar3. Increment both $ar0 and $ar3.
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void sl(const UDSPInstruction& opc)
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{
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u8 areg = (opc.hex & 0x1) + DSP_REG_ACM0;
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dsp_dmem_write(g_dsp.r[0x00], g_dsp.r[areg]);
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dsp_increment_addr_reg(0x00);
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currentEpilogeFunc = sl_epi;
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}
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void sl_epi(const UDSPInstruction& opc)
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{
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u8 dreg = ((opc.hex >> 4) & 0x3) + 0x18;
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const u8 sreg = 0x03;
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u16 val = dsp_dmem_read(g_dsp.r[sreg]);
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dsp_op_write_reg(dreg, val);
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dsp_increment_addr_reg(sreg);
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}
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// SLN $acS.m, $acD.l
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// xxxx xxxx 10dd 011s
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// Store value from register $acS.m to memory location pointed by register
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// $ar0. Load register $acD.l with value from memory pointed by register
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// $ar3. Add corresponding indexing register $ix0 to addressing register $ar0
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// and increment $ar3.
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void sln(const UDSPInstruction& opc)
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{
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u8 areg = (opc.hex & 0x1) + DSP_REG_ACM0;
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dsp_dmem_write(g_dsp.r[0x00], g_dsp.r[areg]);
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dsp_increase_addr_reg(0x00, (s16)g_dsp.r[DSP_REG_IX0]);
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currentEpilogeFunc = sln_epi;
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}
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void sln_epi(const UDSPInstruction& opc)
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{
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u8 dreg = ((opc.hex >> 4) & 0x3) + 0x18;
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const u8 sreg = 0x03;
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u16 val = dsp_dmem_read(g_dsp.r[sreg]);
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dsp_op_write_reg(dreg, val);
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dsp_increment_addr_reg(sreg);
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}
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// SLM $acS.m, $acD.l
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// xxxx xxxx 10dd 101s
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// Store value from register $acS.m to memory location pointed by register
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// $ar0. Load register $acD.l with value from memory pointed by register
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// $ar3. Add corresponding indexing register $ix3 to addressing register $ar3
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// and increment $ar0.
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void slm(const UDSPInstruction& opc)
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{
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u8 areg = (opc.hex & 0x1) + DSP_REG_ACM0;
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dsp_dmem_write(g_dsp.r[0x00], g_dsp.r[areg]);
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dsp_increment_addr_reg(0x00);
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currentEpilogeFunc = slm_epi;
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}
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void slm_epi(const UDSPInstruction& opc)
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{
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u8 dreg = ((opc.hex >> 4) & 0x3) + 0x18;
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const u8 sreg = 0x03;
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u16 val = dsp_dmem_read(g_dsp.r[sreg]);
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dsp_op_write_reg(dreg, val);
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dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
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}
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// SLMN $acS.m, $acD.l
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// xxxx xxxx 10dd 111s
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// Store value from register $acS.m to memory location pointed by register
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// $ar0. Load register $acD.l with value from memory pointed by register
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// $ar3. Add corresponding indexing register $ix0 to addressing register $ar0
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// and add corresponding indexing register $ix3 to addressing register $ar3.
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void slnm(const UDSPInstruction& opc)
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{
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u8 areg = (opc.hex & 0x1) + DSP_REG_ACM0;
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dsp_dmem_write(g_dsp.r[0x00], g_dsp.r[areg]);
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dsp_increase_addr_reg(0x00, (s16)g_dsp.r[DSP_REG_IX0]);
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currentEpilogeFunc = slnm_epi;
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}
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void slnm_epi(const UDSPInstruction& opc)
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{
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u8 dreg = ((opc.hex >> 4) & 0x3) + 0x18;
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const u8 sreg = 0x03;
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u16 val = dsp_dmem_read(g_dsp.r[sreg]);
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dsp_op_write_reg(dreg, val);
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dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
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}
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// Not in duddie's doc
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// LD $ax0.d $ax1.r @$arS
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// xxxx xxxx 11dr 00ss
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void ld(const UDSPInstruction& opc)
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{
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u8 dreg = (opc.hex >> 5) & 0x1;
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u8 rreg = (opc.hex >> 4) & 0x1;
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u8 sreg = opc.hex & 0x3;
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if (sreg != 0x03) {
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g_dsp.r[(dreg << 1) + DSP_REG_AXL0] = dsp_dmem_read(g_dsp.r[sreg]);
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g_dsp.r[(rreg << 1) + DSP_REG_AXL1] = dsp_dmem_read(g_dsp.r[sreg]);
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dsp_increment_addr_reg(sreg);
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} else {
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g_dsp.r[rreg + DSP_REG_AXL0] = dsp_dmem_read(g_dsp.r[dreg]);
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g_dsp.r[rreg + DSP_REG_AXH0] = dsp_dmem_read(g_dsp.r[dreg]);
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dsp_increment_addr_reg(dreg);
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}
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dsp_increment_addr_reg(DSP_REG_AR3);
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}
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// Not in duddie's doc
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// LDN $ax0.d $ax1.r @$arS
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// xxxx xxxx 11dr 01ss
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void ldn(const UDSPInstruction& opc)
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{
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u8 dreg = (opc.hex >> 5) & 0x1;
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u8 rreg = (opc.hex >> 4) & 0x1;
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u8 sreg = opc.hex & 0x3;
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if (sreg != 0x03) {
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g_dsp.r[(dreg << 1) + DSP_REG_AXL0] = dsp_dmem_read(g_dsp.r[sreg]);
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g_dsp.r[(rreg << 1) + DSP_REG_AXL1] = dsp_dmem_read(g_dsp.r[sreg]);
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dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
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} else {
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g_dsp.r[rreg + DSP_REG_AXL0] = dsp_dmem_read(g_dsp.r[dreg]);
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g_dsp.r[rreg + DSP_REG_AXH0] = dsp_dmem_read(g_dsp.r[dreg]);
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dsp_increase_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + dreg]);
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}
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dsp_increment_addr_reg(DSP_REG_AR3);
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}
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// Not in duddie's doc
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// LDM $ax0.d $ax1.r @$arS
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// xxxx xxxx 11dr 10ss
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void ldm(const UDSPInstruction& opc)
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{
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u8 dreg = (opc.hex >> 5) & 0x1;
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u8 rreg = (opc.hex >> 4) & 0x1;
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u8 sreg = opc.hex & 0x3;
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if (sreg != 0x03) {
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g_dsp.r[(dreg << 1) + DSP_REG_AXL0] = dsp_dmem_read(g_dsp.r[sreg]);
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g_dsp.r[(rreg << 1) + DSP_REG_AXL1] = dsp_dmem_read(g_dsp.r[sreg]);
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dsp_increment_addr_reg(sreg);
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} else {
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g_dsp.r[rreg + DSP_REG_AXL0] = dsp_dmem_read(g_dsp.r[dreg]);
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g_dsp.r[rreg + DSP_REG_AXH0] = dsp_dmem_read(g_dsp.r[dreg]);
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dsp_increment_addr_reg(dreg);
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}
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dsp_increase_addr_reg(DSP_REG_AR3, (s16)g_dsp.r[DSP_REG_IX0 + DSP_REG_AR3]);
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}
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// Not in duddie's doc
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// LDNM $ax0.d $ax1.r @$arS
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// xxxx xxxx 11dr 11ss
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void ldnm(const UDSPInstruction& opc)
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{
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u8 dreg = (opc.hex >> 5) & 0x1;
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u8 rreg = (opc.hex >> 4) & 0x1;
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u8 sreg = opc.hex & 0x3;
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if (sreg != 0x03) {
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g_dsp.r[(dreg << 1) + DSP_REG_AXL0] = dsp_dmem_read(g_dsp.r[sreg]);
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g_dsp.r[(rreg << 1) + DSP_REG_AXL1] = dsp_dmem_read(g_dsp.r[sreg]);
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dsp_increase_addr_reg(sreg, (s16)g_dsp.r[DSP_REG_IX0 + sreg]);
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} else {
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g_dsp.r[rreg + DSP_REG_AXL0] = dsp_dmem_read(g_dsp.r[dreg]);
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g_dsp.r[rreg + DSP_REG_AXH0] = dsp_dmem_read(g_dsp.r[dreg]);
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dsp_increase_addr_reg(dreg, (s16)g_dsp.r[DSP_REG_IX0 + dreg]);
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}
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dsp_increase_addr_reg(DSP_REG_AR3, (s16)g_dsp.r[DSP_REG_IX0 + DSP_REG_AR3]);
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}
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void nop(const UDSPInstruction& opc)
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{
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}
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} // end namespace ext
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} // end namespace DSPInterpeter
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