372 lines
10 KiB
C++
372 lines
10 KiB
C++
// Copyright 2008 Dolphin Emulator Project
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// Copyright 2004 Duddie & Tratax
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// Licensed under GPLv2+
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// Refer to the license.txt file included.
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#include "Core/DSP/DSPHWInterface.h"
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#include <atomic>
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#include <cstddef>
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#include <cstring>
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#include "Common/CPUDetect.h"
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#include "Common/CommonTypes.h"
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#include "Common/Intrinsics.h"
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#include "Common/Logging/Log.h"
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#include "Common/MemoryUtil.h"
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#include "Common/Swap.h"
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#include "Core/DSP/DSPAccelerator.h"
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#include "Core/DSP/DSPCore.h"
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#include "Core/DSP/DSPHost.h"
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#include "Core/DSP/DSPTables.h"
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namespace DSP
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{
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static void gdsp_do_dma();
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void gdsp_ifx_init()
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{
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g_dsp.ifx_regs.fill(0);
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g_dsp.mbox[MAILBOX_CPU].store(0);
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g_dsp.mbox[MAILBOX_DSP].store(0);
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}
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u32 gdsp_mbox_peek(Mailbox mbx)
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{
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return g_dsp.mbox[mbx].load();
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}
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void gdsp_mbox_write_h(Mailbox mbx, u16 val)
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{
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const u32 old_value = g_dsp.mbox[mbx].load(std::memory_order_acquire);
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const u32 new_value = (old_value & 0xffff) | (val << 16);
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g_dsp.mbox[mbx].store(new_value & ~0x80000000, std::memory_order_release);
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}
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void gdsp_mbox_write_l(Mailbox mbx, u16 val)
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{
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const u32 old_value = g_dsp.mbox[mbx].load(std::memory_order_acquire);
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const u32 new_value = (old_value & ~0xffff) | val;
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g_dsp.mbox[mbx].store(new_value | 0x80000000, std::memory_order_release);
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#if defined(_DEBUG) || defined(DEBUGFAST)
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const char* const type = mbx == MAILBOX_DSP ? "DSP" : "CPU";
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DEBUG_LOG_FMT(DSP_MAIL, "{}(WM) B:{} M:{:#010x} (pc={:#06x})", type, mbx, gdsp_mbox_peek(mbx),
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g_dsp.pc);
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#endif
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}
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u16 gdsp_mbox_read_h(Mailbox mbx)
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{
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if (g_init_hax && mbx == MAILBOX_DSP)
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{
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return 0x8054;
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}
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return (u16)(g_dsp.mbox[mbx].load() >> 16); // TODO: mask away the top bit?
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}
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u16 gdsp_mbox_read_l(Mailbox mbx)
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{
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const u32 value = g_dsp.mbox[mbx].load(std::memory_order_acquire);
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g_dsp.mbox[mbx].store(value & ~0x80000000, std::memory_order_release);
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if (g_init_hax && mbx == MAILBOX_DSP)
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{
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g_init_hax = false;
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DSPCore_Reset();
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return 0x4348;
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}
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#if defined(_DEBUG) || defined(DEBUGFAST)
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const char* const type = mbx == MAILBOX_DSP ? "DSP" : "CPU";
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DEBUG_LOG_FMT(DSP_MAIL, "{}(RM) B:{} M:0x{:#010x} (pc={:#06x})", type, mbx, gdsp_mbox_peek(mbx),
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g_dsp.pc);
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#endif
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return (u16)value;
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}
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void gdsp_ifx_write(u32 addr, u16 val)
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{
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g_dsp_cap->LogIFXWrite(addr, val);
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switch (addr & 0xff)
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{
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case DSP_DIRQ:
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if ((val & 1) != 0)
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Host::InterruptRequest();
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else
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WARN_LOG_FMT(DSPLLE, "Unknown Interrupt Request pc={:#06x} ({:#06x})", g_dsp.pc, val);
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break;
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case DSP_DMBH:
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gdsp_mbox_write_h(MAILBOX_DSP, val);
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break;
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case DSP_DMBL:
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gdsp_mbox_write_l(MAILBOX_DSP, val);
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break;
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case DSP_CMBH:
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return gdsp_mbox_write_h(MAILBOX_CPU, val);
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case DSP_CMBL:
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return gdsp_mbox_write_l(MAILBOX_CPU, val);
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case DSP_DSBL:
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g_dsp.ifx_regs[DSP_DSBL] = val;
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g_dsp.ifx_regs[DSP_DSCR] |= 4; // Doesn't really matter since we do DMA instantly
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if (!g_dsp.ifx_regs[DSP_AMDM])
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gdsp_do_dma();
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else
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NOTICE_LOG_FMT(DSPLLE, "Masked DMA skipped");
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g_dsp.ifx_regs[DSP_DSCR] &= ~4;
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g_dsp.ifx_regs[DSP_DSBL] = 0;
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break;
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case DSP_GAIN:
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if (val != 0)
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{
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DEBUG_LOG_FMT(DSPLLE, "Gain Written: {:#06x}", val);
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}
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[[fallthrough]];
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case DSP_DSPA:
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case DSP_DSMAH:
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case DSP_DSMAL:
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case DSP_DSCR:
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g_dsp.ifx_regs[addr & 0xFF] = val;
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break;
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case DSP_ACSAH:
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g_dsp.accelerator->SetStartAddress(val << 16 |
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static_cast<u16>(g_dsp.accelerator->GetStartAddress()));
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break;
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case DSP_ACSAL:
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g_dsp.accelerator->SetStartAddress(
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static_cast<u16>(g_dsp.accelerator->GetStartAddress() >> 16) << 16 | val);
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break;
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case DSP_ACEAH:
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g_dsp.accelerator->SetEndAddress(val << 16 |
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static_cast<u16>(g_dsp.accelerator->GetEndAddress()));
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break;
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case DSP_ACEAL:
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g_dsp.accelerator->SetEndAddress(
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static_cast<u16>(g_dsp.accelerator->GetEndAddress() >> 16) << 16 | val);
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break;
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case DSP_ACCAH:
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g_dsp.accelerator->SetCurrentAddress(val << 16 |
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static_cast<u16>(g_dsp.accelerator->GetCurrentAddress()));
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break;
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case DSP_ACCAL:
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g_dsp.accelerator->SetCurrentAddress(
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static_cast<u16>(g_dsp.accelerator->GetCurrentAddress() >> 16) << 16 | val);
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break;
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case DSP_FORMAT:
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g_dsp.accelerator->SetSampleFormat(val);
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break;
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case DSP_YN1:
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g_dsp.accelerator->SetYn1(val);
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break;
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case DSP_YN2:
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g_dsp.accelerator->SetYn2(val);
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break;
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case DSP_PRED_SCALE:
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g_dsp.accelerator->SetPredScale(val);
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break;
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case DSP_ACDATA1: // Accelerator write (Zelda type) - "UnkZelda"
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g_dsp.accelerator->WriteD3(val);
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break;
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default:
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if ((addr & 0xff) >= 0xa0)
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{
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const u32 index = (addr & 0xFF) - 0xa0;
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const auto& label = pdlabels[index];
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if (label.name && label.description)
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{
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DEBUG_LOG_FMT(DSPLLE, "{:04x} MW {} ({:04x})", g_dsp.pc, label.name, val);
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}
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else
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{
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ERROR_LOG_FMT(DSPLLE, "{:04x} MW {:04x} ({:04x})", g_dsp.pc, addr, val);
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}
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}
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else
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{
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ERROR_LOG_FMT(DSPLLE, "{:04x} MW {:04x} ({:04x})", g_dsp.pc, addr, val);
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}
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g_dsp.ifx_regs[addr & 0xFF] = val;
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break;
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}
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}
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static u16 _gdsp_ifx_read(u16 addr)
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{
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switch (addr & 0xff)
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{
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case DSP_DMBH:
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return gdsp_mbox_read_h(MAILBOX_DSP);
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case DSP_DMBL:
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return gdsp_mbox_read_l(MAILBOX_DSP);
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case DSP_CMBH:
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return gdsp_mbox_read_h(MAILBOX_CPU);
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case DSP_CMBL:
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return gdsp_mbox_read_l(MAILBOX_CPU);
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case DSP_DSCR:
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return g_dsp.ifx_regs[addr & 0xFF];
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case DSP_ACSAH:
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return static_cast<u16>(g_dsp.accelerator->GetStartAddress() >> 16);
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case DSP_ACSAL:
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return static_cast<u16>(g_dsp.accelerator->GetStartAddress());
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case DSP_ACEAH:
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return static_cast<u16>(g_dsp.accelerator->GetEndAddress() >> 16);
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case DSP_ACEAL:
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return static_cast<u16>(g_dsp.accelerator->GetEndAddress());
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case DSP_ACCAH:
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return static_cast<u16>(g_dsp.accelerator->GetCurrentAddress() >> 16);
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case DSP_ACCAL:
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return static_cast<u16>(g_dsp.accelerator->GetCurrentAddress());
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case DSP_FORMAT:
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return g_dsp.accelerator->GetSampleFormat();
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case DSP_YN1:
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return g_dsp.accelerator->GetYn1();
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case DSP_YN2:
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return g_dsp.accelerator->GetYn2();
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case DSP_PRED_SCALE:
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return g_dsp.accelerator->GetPredScale();
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case DSP_ACCELERATOR: // ADPCM Accelerator reads
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return g_dsp.accelerator->Read(reinterpret_cast<s16*>(&g_dsp.ifx_regs[DSP_COEF_A1_0]));
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case DSP_ACDATA1: // Accelerator reads (Zelda type) - "UnkZelda"
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return g_dsp.accelerator->ReadD3();
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default:
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{
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const u16 ifx_reg = g_dsp.ifx_regs[addr & 0xFF];
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if ((addr & 0xff) >= 0xa0)
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{
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const u32 index = (addr & 0xFF) - 0xa0;
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const auto& label = pdlabels[index];
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if (label.name && label.description)
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{
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DEBUG_LOG_FMT(DSPLLE, "{:04x} MR {} ({:04x})", g_dsp.pc, label.name, ifx_reg);
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}
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else
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{
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ERROR_LOG_FMT(DSPLLE, "{:04x} MR {:04x} ({:04x})", g_dsp.pc, addr, ifx_reg);
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}
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}
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else
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{
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ERROR_LOG_FMT(DSPLLE, "{:04x} MR {:04x} ({:04x})", g_dsp.pc, addr, ifx_reg);
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}
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return ifx_reg;
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}
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}
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}
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u16 gdsp_ifx_read(u16 addr)
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{
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u16 retval = _gdsp_ifx_read(addr);
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g_dsp_cap->LogIFXRead(addr, retval);
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return retval;
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}
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static const u8* gdsp_idma_in(u16 dsp_addr, u32 addr, u32 size)
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{
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Common::UnWriteProtectMemory(g_dsp.iram, DSP_IRAM_BYTE_SIZE, false);
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Host::DMAToDSP(g_dsp.iram + dsp_addr / 2, addr, size);
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Common::WriteProtectMemory(g_dsp.iram, DSP_IRAM_BYTE_SIZE, false);
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Host::CodeLoaded(addr, size);
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NOTICE_LOG_FMT(DSPLLE, "*** Copy new UCode from {:#010x} to {:#06x} (crc: {:#08x})", addr,
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dsp_addr, g_dsp.iram_crc);
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return reinterpret_cast<u8*>(g_dsp.iram) + dsp_addr;
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}
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static const u8* gdsp_idma_out(u16 dsp_addr, u32 addr, u32 size)
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{
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ERROR_LOG_FMT(DSPLLE, "*** idma_out IRAM_DSP ({:#06x}) -> RAM ({:#010x}) : size ({:#010x})",
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dsp_addr / 2, addr, size);
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return nullptr;
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}
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// TODO: These should eat clock cycles.
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static const u8* gdsp_ddma_in(u16 dsp_addr, u32 addr, u32 size)
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{
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Host::DMAToDSP(g_dsp.dram + dsp_addr / 2, addr, size);
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DEBUG_LOG_FMT(DSPLLE, "*** ddma_in RAM ({:#010x}) -> DRAM_DSP ({:#06x}) : size ({:#010x})", addr,
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dsp_addr / 2, size);
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return reinterpret_cast<u8*>(g_dsp.dram) + dsp_addr;
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}
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static const u8* gdsp_ddma_out(u16 dsp_addr, u32 addr, u32 size)
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{
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Host::DMAFromDSP(g_dsp.dram + dsp_addr / 2, addr, size);
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DEBUG_LOG_FMT(DSPLLE, "*** ddma_out DRAM_DSP ({:#06x}) -> RAM ({:#010x}) : size ({:#010x})",
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dsp_addr / 2, addr, size);
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return reinterpret_cast<const u8*>(g_dsp.dram) + dsp_addr;
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}
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static void gdsp_do_dma()
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{
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const u32 addr = (g_dsp.ifx_regs[DSP_DSMAH] << 16) | g_dsp.ifx_regs[DSP_DSMAL];
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const u16 ctl = g_dsp.ifx_regs[DSP_DSCR];
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const u16 dsp_addr = g_dsp.ifx_regs[DSP_DSPA] * 2;
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const u16 len = g_dsp.ifx_regs[DSP_DSBL];
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if (len > 0x4000)
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{
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ERROR_LOG_FMT(DSPLLE,
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"DMA ERROR: PC: {:04x}, Control: {:04x}, Address: {:08x}, DSP Address: {:04x}, "
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"Size: {:04x}",
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g_dsp.pc, ctl, addr, dsp_addr, len);
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std::exit(0);
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}
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#if defined(_DEBUG) || defined(DEBUGFAST)
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DEBUG_LOG_FMT(
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DSPLLE, "DMA pc: {:04x}, Control: {:04x}, Address: {:08x}, DSP Address: {:04x}, Size: {:04x}",
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g_dsp.pc, ctl, addr, dsp_addr, len);
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#endif
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const u8* copied_data_ptr = nullptr;
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switch (ctl & 0x3)
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{
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case (DSP_CR_DMEM | DSP_CR_TO_CPU):
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copied_data_ptr = gdsp_ddma_out(dsp_addr, addr, len);
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break;
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case (DSP_CR_DMEM | DSP_CR_FROM_CPU):
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copied_data_ptr = gdsp_ddma_in(dsp_addr, addr, len);
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break;
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case (DSP_CR_IMEM | DSP_CR_TO_CPU):
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copied_data_ptr = gdsp_idma_out(dsp_addr, addr, len);
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break;
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case (DSP_CR_IMEM | DSP_CR_FROM_CPU):
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copied_data_ptr = gdsp_idma_in(dsp_addr, addr, len);
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break;
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}
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if (copied_data_ptr)
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g_dsp_cap->LogDMA(ctl, addr, dsp_addr, len, copied_data_ptr);
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}
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} // namespace DSP
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