81 lines
2.4 KiB
C++
81 lines
2.4 KiB
C++
// Copyright 2013 Dolphin Emulator Project
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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#pragma once
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#include "Common.h"
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#include <intrin.h>
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#include <Windows.h>
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// Atomic operations are performed in a single step by the CPU. It is
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// impossible for other threads to see the operation "half-done."
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//
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// Some atomic operations can be combined with different types of memory
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// barriers called "Acquire semantics" and "Release semantics", defined below.
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//
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// Acquire semantics: Future memory accesses cannot be relocated to before the
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// operation.
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//
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// Release semantics: Past memory accesses cannot be relocated to after the
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// operation.
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//
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// These barriers affect not only the compiler, but also the CPU.
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//
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// NOTE: Acquire and Release are not differentiated right now. They perform a
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// full memory barrier instead of a "one-way" memory barrier. The newest
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// Windows SDK has Acquire and Release versions of some Interlocked* functions.
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namespace Common
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{
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inline void AtomicAdd(volatile u32& target, u32 value) {
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_InterlockedExchangeAdd((volatile LONG*)&target, (LONG)value);
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}
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inline void AtomicAnd(volatile u32& target, u32 value) {
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_InterlockedAnd((volatile LONG*)&target, (LONG)value);
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}
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inline void AtomicIncrement(volatile u32& target) {
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_InterlockedIncrement((volatile LONG*)&target);
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}
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inline void AtomicDecrement(volatile u32& target) {
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_InterlockedDecrement((volatile LONG*)&target);
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}
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inline void AtomicOr(volatile u32& target, u32 value) {
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_InterlockedOr((volatile LONG*)&target, (LONG)value);
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}
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template <typename T>
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inline T AtomicLoad(volatile T& src) {
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return src; // 32-bit reads are always atomic.
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}
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template <typename T>
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inline T AtomicLoadAcquire(volatile T& src) {
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T result = src; // 32-bit reads are always atomic.
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_ReadBarrier(); // Compiler instruction only. x86 loads always have acquire semantics.
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return result;
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}
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template <typename T, typename U>
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inline void AtomicStore(volatile T& dest, U value) {
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dest = (T) value; // 32-bit writes are always atomic.
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}
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template <typename T, typename U>
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inline void AtomicStoreRelease(volatile T& dest, U value) {
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_WriteBarrier(); // Compiler instruction only. x86 stores always have release semantics.
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dest = (T) value; // 32-bit writes are always atomic.
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}
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template <typename T, typename U>
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inline T* AtomicExchangeAcquire(T* volatile& loc, U newval) {
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return (T*) _InterlockedExchangePointer_acq((void* volatile*) &loc, (void*) newval);
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}
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}
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