155 lines
3.7 KiB
C++
155 lines
3.7 KiB
C++
// Copyright 2013 Dolphin Emulator Project
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// Licensed under GPLv2
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// Refer to the license.txt file included.
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#pragma once
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#include "Common/CommonTypes.h"
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#include "VideoCommon/VideoBackendBase.h"
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class PointerWrap;
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namespace MMIO { class Mapping; }
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extern bool MT;
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namespace CommandProcessor
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{
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extern SCPFifoStruct fifo; //This one is shared between gfx thread and emulator thread.
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extern volatile bool isPossibleWaitingSetDrawDone; //This one is used for sync gfx thread and emulator thread.
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extern volatile bool interruptSet;
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extern volatile bool interruptWaiting;
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extern volatile bool interruptTokenWaiting;
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extern volatile bool interruptFinishWaiting;
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// internal hardware addresses
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enum
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{
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STATUS_REGISTER = 0x00,
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CTRL_REGISTER = 0x02,
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CLEAR_REGISTER = 0x04,
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PERF_SELECT = 0x06,
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FIFO_TOKEN_REGISTER = 0x0E,
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FIFO_BOUNDING_BOX_LEFT = 0x10,
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FIFO_BOUNDING_BOX_RIGHT = 0x12,
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FIFO_BOUNDING_BOX_TOP = 0x14,
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FIFO_BOUNDING_BOX_BOTTOM = 0x16,
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FIFO_BASE_LO = 0x20,
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FIFO_BASE_HI = 0x22,
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FIFO_END_LO = 0x24,
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FIFO_END_HI = 0x26,
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FIFO_HI_WATERMARK_LO = 0x28,
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FIFO_HI_WATERMARK_HI = 0x2a,
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FIFO_LO_WATERMARK_LO = 0x2c,
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FIFO_LO_WATERMARK_HI = 0x2e,
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FIFO_RW_DISTANCE_LO = 0x30,
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FIFO_RW_DISTANCE_HI = 0x32,
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FIFO_WRITE_POINTER_LO = 0x34,
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FIFO_WRITE_POINTER_HI = 0x36,
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FIFO_READ_POINTER_LO = 0x38,
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FIFO_READ_POINTER_HI = 0x3A,
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FIFO_BP_LO = 0x3C,
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FIFO_BP_HI = 0x3E,
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XF_RASBUSY_L = 0x40,
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XF_RASBUSY_H = 0x42,
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XF_CLKS_L = 0x44,
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XF_CLKS_H = 0x46,
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XF_WAIT_IN_L = 0x48,
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XF_WAIT_IN_H = 0x4a,
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XF_WAIT_OUT_L = 0x4c,
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XF_WAIT_OUT_H = 0x4e,
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VCACHE_METRIC_CHECK_L = 0x50,
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VCACHE_METRIC_CHECK_H = 0x52,
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VCACHE_METRIC_MISS_L = 0x54,
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VCACHE_METRIC_MISS_H = 0x56,
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VCACHE_METRIC_STALL_L = 0x58,
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VCACHE_METRIC_STALL_H = 0x5A,
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CLKS_PER_VTX_IN_L = 0x60,
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CLKS_PER_VTX_IN_H = 0x62,
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CLKS_PER_VTX_OUT = 0x64,
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};
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enum
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{
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GATHER_PIPE_SIZE = 32,
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INT_CAUSE_CP = 0x800
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};
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// Fifo Status Register
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union UCPStatusReg
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{
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struct
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{
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u16 OverflowHiWatermark : 1;
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u16 UnderflowLoWatermark : 1;
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u16 ReadIdle : 1;
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u16 CommandIdle : 1;
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u16 Breakpoint : 1;
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u16 : 11;
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};
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u16 Hex;
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UCPStatusReg() {Hex = 0; }
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UCPStatusReg(u16 _hex) {Hex = _hex; }
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};
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// Fifo Control Register
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union UCPCtrlReg
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{
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struct
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{
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u16 GPReadEnable : 1;
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u16 BPEnable : 1;
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u16 FifoOverflowIntEnable : 1;
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u16 FifoUnderflowIntEnable : 1;
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u16 GPLinkEnable : 1;
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u16 BPInt : 1;
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u16 : 10;
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};
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u16 Hex;
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UCPCtrlReg() {Hex = 0; }
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UCPCtrlReg(u16 _hex) {Hex = _hex; }
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};
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// Fifo Clear Register
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union UCPClearReg
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{
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struct
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{
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u16 ClearFifoOverflow : 1;
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u16 ClearFifoUnderflow : 1;
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u16 ClearMetrices : 1;
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u16 : 13;
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};
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u16 Hex;
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UCPClearReg() {Hex = 0; }
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UCPClearReg(u16 _hex) {Hex = _hex; }
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};
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// Can be any number, low enough to not be below the number of clocks executed by the GPU per CP_PERIOD
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const static u32 m_cpClockOrigin = 200000;
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// Init
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void Init();
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void Shutdown();
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void DoState(PointerWrap &p);
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void RegisterMMIO(MMIO::Mapping* mmio, u32 base);
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void SetCPStatusFromGPU();
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void SetCPStatusFromCPU();
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void GatherPipeBursted();
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void UpdateInterrupts(u64 userdata);
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void UpdateInterruptsFromVideoBackend(u64 userdata);
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void SetCpClearRegister();
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void SetCpControlRegister();
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void SetCpStatusRegister();
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void ProcessFifoAllDistance();
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void ProcessFifoEvents();
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void Update();
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extern volatile u32 VITicks;
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} // namespace CommandProcessor
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