870 lines
19 KiB
C++
870 lines
19 KiB
C++
// Copyright (C) 2003 Dolphin Project.
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, version 2.0.
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License 2.0 for more details.
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// A copy of the GPL 2.0 should have been included with the program.
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// If not, see http://www.gnu.org/licenses/
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// Official SVN repository and contact information can be found at
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// http://code.google.com/p/dolphin-emu/
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// Additional copyrights go to Duddie and Tratax (c) 2004
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#include "DSPInterpreter.h"
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#include "DSPIntCCUtil.h"
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#include "DSPIntUtil.h"
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// Arithmetic and accumulator control.
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namespace DSPInterpreter {
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// CLR $acR
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// 1000 r001 xxxx xxxx
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// Clears accumulator $acR
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void clr(const UDSPInstruction& opc)
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{
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u8 reg = (opc.hex >> 11) & 0x1;
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dsp_set_long_acc(reg, 0);
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Update_SR_Register64((s64)0); // really?
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zeroWriteBackLog();
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}
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// CLRL $acR.l
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// 1111 110r xxxx xxxx
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// Clears $acR.l - low 16 bits of accumulator $acR.
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void clrl(const UDSPInstruction& opc)
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{
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u16 reg = DSP_REG_ACL0 + ((opc.hex >> 8) & 0x1);
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g_dsp.r[reg] = 0;
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// Should this be 64bit?
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// nakee: it says the whole reg in duddie's doc sounds weird
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Update_SR_Register64((s64)reg);
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zeroWriteBackLog();
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}
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// ADDAXL $acD, $axS.l
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// 0111 00sd xxxx xxxx
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// Adds secondary accumulator $axS.l to accumulator register $acD.
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void addaxl(const UDSPInstruction& opc)
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{
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u8 sreg = (opc.hex >> 9) & 0x1;
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u8 dreg = (opc.hex >> 8) & 0x1;
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s64 acc = dsp_get_long_acc(dreg);
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s64 acx = dsp_get_ax_l(sreg);
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acc += acx;
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zeroWriteBackLog();
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dsp_set_long_acc(dreg, acc);
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Update_SR_Register64(acc);
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}
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// TSTAXH $axR.h
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// 1000 011r xxxx xxxx
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// Test high part of secondary accumulator $axR.h.
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void tstaxh(const UDSPInstruction& opc)
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{
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u8 reg = (opc.hex >> 8) & 0x1;
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s16 val = dsp_get_ax_h(reg);
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Update_SR_Register16(val);
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zeroWriteBackLog();
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}
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// SUB $acD, $ac(1-D)
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// 0101 110d xxxx xxxx
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// Subtracts accumulator $ac(1-D) from accumulator register $acD.
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void sub(const UDSPInstruction& opc)
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{
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u8 D = (opc.hex >> 8) & 0x1;
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s64 acc1 = dsp_get_long_acc(D);
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s64 acc2 = dsp_get_long_acc(1 - D);
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acc1 -= acc2;
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zeroWriteBackLog();
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dsp_set_long_acc(D, acc1);
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Update_SR_Register64(acc1);
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}
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// MOVR $acD, $axS.R
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// 0110 0srd xxxx xxxx
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// Moves register $axS.R (sign extended) to middle accumulator $acD.hm.
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// Sets $acD.l to 0.
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// TODO: Check what happens to acD.h.
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void movr(const UDSPInstruction& opc)
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{
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u8 areg = (opc.hex >> 8) & 0x1;
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u8 sreg = ((opc.hex >> 9) & 0x3) + DSP_REG_AXL0;
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s64 acc = (s16)g_dsp.r[sreg];
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acc <<= 16;
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acc &= ~0xffff;
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zeroWriteBackLog();
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dsp_set_long_acc(areg, acc);
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Update_SR_Register64(acc);
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}
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// MOVAX $acD, $axS
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// 0110 10sd xxxx xxxx
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// Moves secondary accumulator $axS to accumulator $axD.
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void movax(const UDSPInstruction& opc)
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{
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u8 dreg = (opc.hex >> 8) & 0x1;
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u8 sreg = (opc.hex >> 9) & 0x1;
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s64 acx = dsp_get_long_acx(sreg);
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zeroWriteBackLog();
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dsp_set_long_acc(dreg, acx);
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Update_SR_Register64(acx);
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}
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// XORR $acD.m, $axS.h
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// 0011 00sd 0xxx xxxx
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// Logic XOR (exclusive or) middle part of accumulator $acD.m with
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// high part of secondary accumulator $axS.h.
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// x = extension (7 bits!!)
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void xorr(const UDSPInstruction& opc)
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{
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u8 sreg = (opc.hex >> 9) & 0x1;
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u8 dreg = (opc.hex >> 8) & 0x1;
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u16 axh = g_dsp.r[DSP_REG_AXH0 + sreg];
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zeroWriteBackLog();
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g_dsp.r[DSP_REG_ACM0 + dreg] ^= axh;
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Update_SR_Register16(dsp_get_acc_m(dreg));
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}
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// ANDR $acD.m, $axS.h
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// 0011 01sd 0xxx xxxx
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// Logic AND middle part of accumulator $acD.m with high part of
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// secondary accumulator $axS.h.
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// x = extension (7 bits!!)
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void andr(const UDSPInstruction& opc)
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{
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u8 sreg = (opc.hex >> 9) & 0x1;
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u8 dreg = (opc.hex >> 8) & 0x1;
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u16 axh = g_dsp.r[DSP_REG_AXH0 + sreg];
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zeroWriteBackLog();
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g_dsp.r[DSP_REG_ACM0 + dreg] &= axh;
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Update_SR_Register16(dsp_get_acc_m(dreg));
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}
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// ORR $acD.m, $axS.h
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// 0011 10sd 0xxx xxxx
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// Logic OR middle part of accumulator $acD.m with high part of
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// secondary accumulator $axS.h.
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// x = extension (7 bits!!)
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void orr(const UDSPInstruction& opc)
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{
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u8 sreg = (opc.hex >> 9) & 0x1;
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u8 dreg = (opc.hex >> 8) & 0x1;
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u16 axh = g_dsp.r[DSP_REG_AXH0 + sreg];
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zeroWriteBackLog();
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g_dsp.r[DSP_REG_ACM0 + dreg] |= axh;
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Update_SR_Register16(dsp_get_acc_m(dreg));
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}
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// ANDC $acD.m, $ac(1-D).m
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// 0011 110d 0xxx xxxx
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// Logic AND middle part of accumulator $acD.m with middle part of
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// accumulator $ac(1-D).m
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// x = extension (7 bits!!)
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void andc(const UDSPInstruction& opc)
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{
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u8 D = (opc.hex >> 8) & 0x1;
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u16 accm = dsp_get_acc_m(1-D);
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zeroWriteBackLog();
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g_dsp.r[DSP_REG_ACM0+D] &= accm;
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Update_SR_Register16(dsp_get_acc_m(D));
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}
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// ORC $acD.m, $ac(1-D).m
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// 0011 111d 0xxx xxxx
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// Logic OR middle part of accumulator $acD.m with middle part of
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// accumulator $ac(1-D).m.
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// x = extension (7 bits!!)
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void orc(const UDSPInstruction& opc)
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{
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u8 D = (opc.hex >> 8) & 0x1;
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u16 accm = dsp_get_acc_m(1-D);
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zeroWriteBackLog();
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g_dsp.r[DSP_REG_ACM0+D] |= accm;
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Update_SR_Register16(dsp_get_acc_m(D));
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}
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// XORC $acD.m
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// 0011 000d 1xxx xxxx
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// Logic XOR (exclusive or) middle part of accumulator $acD.m with $ac(1-D).m
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// x = extension (7 bits!!)
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void xorc(const UDSPInstruction& opc)
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{
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u8 dreg = (opc.hex >> 8) & 0x1;
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u16 res = dsp_get_acc_m(dreg) ^ dsp_get_acc_m(1 - dreg);
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zeroWriteBackLog();
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g_dsp.r[DSP_REG_ACM0 + dreg] = res;
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Update_SR_Register16(res);
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}
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// NOT $acD.m
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// 0011 001d 1xxx xxxx
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// Invert all bits in dest reg, aka xor with 0xffff
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// x = extension (7 bits!!)
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void notc(const UDSPInstruction& opc)
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{
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u8 dreg = (opc.hex >> 8) & 0x1;
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u16 res = dsp_get_acc_m(dreg)^0xffff;
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zeroWriteBackLog();
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g_dsp.r[DSP_REG_ACM0 + dreg] = res;
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Update_SR_Register16(res);
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}
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void orf(const UDSPInstruction& opc)
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{
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ERROR_LOG(DSPLLE, "orf not implemented");
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}
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// Hermes switched andf and andcf, so check to make sure they are still correct
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// ANDCF $acD.m, #I
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// 0000 001r 1100 0000
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// iiii iiii iiii iiii
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// Set logic zero (LZ) flag in status register $sr if result of logic AND of
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// accumulator mid part $acD.m with immediate value I is equal I.
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void andcf(const UDSPInstruction& opc)
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{
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u8 reg = (opc.hex >> 8) & 0x1;
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u16 imm = dsp_fetch_code();
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u16 val = dsp_get_acc_m(reg);
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Update_SR_LZ(((val & imm) == imm) ? 0 : 1);
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}
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// Hermes switched andf and andcf, so check to make sure they are still correct
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// ANDF $acD.m, #I
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// 0000 001r 1010 0000
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// iiii iiii iiii iiii
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// Set logic zero (LZ) flag in status register $sr if result of logical AND
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// operation of accumulator mid part $acD.m with immediate value I is equal
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// immediate value 0.
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void andf(const UDSPInstruction& opc)
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{
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u8 reg = (opc.hex >> 8) & 0x1;
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u16 imm = dsp_fetch_code();
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u16 val = dsp_get_acc_m(reg);
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Update_SR_LZ(((val & imm) == 0) ? 0 : 1);
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}
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// CMPI $amD, #I
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// 0000 001r 1000 0000
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// iiii iiii iiii iiii
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// Compares mid accumulator $acD.hm ($amD) with sign extended immediate value I.
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// Although flags are being set regarding whole accumulator register.
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void cmpi(const UDSPInstruction& opc)
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{
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int reg = (opc.hex >> 8) & 0x1;
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// Immediate is considered to be at M level in the 40-bit accumulator.
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s64 imm = (s64)(s16)dsp_fetch_code() << 16;
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s64 val = dsp_get_long_acc(reg);
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Update_SR_Register64(val - imm);
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}
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// XORI $acD.m, #I
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// 0000 001r 0010 0000
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// iiii iiii iiii iiii
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// Logic exclusive or (XOR) of accumulator mid part $acD.m with
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// immediate value I.
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void xori(const UDSPInstruction& opc)
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{
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u8 reg = DSP_REG_ACM0 + ((opc.hex >> 8) & 0x1);
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u16 imm = dsp_fetch_code();
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g_dsp.r[reg] ^= imm;
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Update_SR_Register16((s16)g_dsp.r[reg]);
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}
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// ANDI $acD.m, #I
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// 0000 001r 0100 0000
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// iiii iiii iiii iiii
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// Logic AND of accumulator mid part $acD.m with immediate value I.
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void andi(const UDSPInstruction& opc)
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{
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u8 reg = DSP_REG_ACM0 + ((opc.hex >> 8) & 0x1);
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u16 imm = dsp_fetch_code();
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g_dsp.r[reg] &= imm;
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Update_SR_Register16((s16)g_dsp.r[reg]);
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}
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// ORI $acD.m, #I
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// 0000 001r 0110 0000
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// iiii iiii iiii iiii
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// Logic OR of accumulator mid part $acD.m with immediate value I.
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void ori(const UDSPInstruction& opc)
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{
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u8 reg = DSP_REG_ACM0 + ((opc.hex >> 8) & 0x1);
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u16 imm = dsp_fetch_code();
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g_dsp.r[reg] |= imm;
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Update_SR_Register16((s16)g_dsp.r[reg]);
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}
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//-------------------------------------------------------------
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// ADD $acD, $ac(1-D)
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// 0100 110d xxxx xxxx
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// Adds accumulator $ac(1-D) to accumulator register $acD.
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void add(const UDSPInstruction& opc)
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{
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u8 areg = (opc.hex >> 8) & 0x1;
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s64 acc0 = dsp_get_long_acc(0);
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s64 acc1 = dsp_get_long_acc(1);
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s64 res = acc0 + acc1;
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zeroWriteBackLog();
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dsp_set_long_acc(areg, res);
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Update_SR_Register64(res);
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}
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// ADDP $acD
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// 0100 111d xxxx xxxx
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// Adds product register to accumulator register.
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void addp(const UDSPInstruction& opc)
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{
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u8 dreg = (opc.hex >> 8) & 0x1;
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s64 acc = dsp_get_long_acc(dreg);
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acc += dsp_get_long_prod();
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zeroWriteBackLog();
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dsp_set_long_acc(dreg, acc);
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Update_SR_Register64(acc);
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}
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// SUBP $acD
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// 0101 111d xxxx xxxx
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// Subtracts product register from accumulator register.
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void subp(const UDSPInstruction& opc)
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{
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u8 dreg = (opc.hex >> 8) & 0x1;
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s64 acc = dsp_get_long_acc(dreg);
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acc -= dsp_get_long_prod();
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zeroWriteBackLog();
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dsp_set_long_acc(dreg, acc);
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Update_SR_Register64(acc);
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}
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// CMPIS $acD, #I
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// 0000 011d iiii iiii
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// Compares accumulator with short immediate. Comaprison is executed
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// by subtracting short immediate (8bit sign extended) from mid accumulator
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// $acD.hm and computing flags based on whole accumulator $acD.
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void cmpis(const UDSPInstruction& opc)
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{
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u8 areg = (opc.hex >> 8) & 0x1;
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s64 acc = dsp_get_long_acc(areg);
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s64 val = (s8)opc.hex;
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val <<= 16;
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s64 res = acc - val;
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Update_SR_Register64(res);
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}
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// DECM $acsD
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// 0111 100d xxxx xxxx
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// Decrement 24-bit mid-accumulator $acsD.
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void decm(const UDSPInstruction& opc)
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{
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u8 dreg = (opc.hex >> 8) & 0x01;
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s64 sub = 0x10000;
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s64 acc = dsp_get_long_acc(dreg);
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acc -= sub;
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zeroWriteBackLog();
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dsp_set_long_acc(dreg, acc);
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Update_SR_Register64(acc);
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}
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// DEC $acD
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// 0111 101d xxxx xxxx
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// Decrement accumulator $acD.
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void dec(const UDSPInstruction& opc)
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{
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u8 dreg = (opc.hex >> 8) & 0x01;
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s64 acc = dsp_get_long_acc(dreg) - 1;
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zeroWriteBackLog();
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dsp_set_long_acc(dreg, acc);
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Update_SR_Register64(acc);
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}
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// INCM $acsD
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// 0111 010d xxxx xxxx
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// Increment 24-bit mid-accumulator $acsD.
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void incm(const UDSPInstruction& opc)
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{
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u8 dreg = (opc.hex >> 8) & 0x1;
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s64 sub = 0x10000;
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s64 acc = dsp_get_long_acc(dreg);
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acc += sub;
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zeroWriteBackLog();
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dsp_set_long_acc(dreg, acc);
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Update_SR_Register64(acc);
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}
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// INC $acD
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// 0111 011d xxxx xxxx
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// Increment accumulator $acD.
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void inc(const UDSPInstruction& opc)
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{
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u8 dreg = (opc.hex >> 8) & 0x1;
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s64 acc = dsp_get_long_acc(dreg) + 1;
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zeroWriteBackLog();
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dsp_set_long_acc(dreg, acc);
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Update_SR_Register64(acc);
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}
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// NEG $acD
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// 0111 110d xxxx xxxx
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// Negate accumulator $acD.
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void neg(const UDSPInstruction& opc)
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{
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u8 areg = (opc.hex >> 8) & 0x1;
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s64 acc = dsp_get_long_acc(areg);
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acc = 0 - acc;
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zeroWriteBackLog();
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dsp_set_long_acc(areg, acc);
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Update_SR_Register64(acc);
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}
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// MOV $acD, $ac(1-D)
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// 0110 110d xxxx xxxx
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// Moves accumulator $ax(1-D) to accumulator $axD.
|
|
void mov(const UDSPInstruction& opc)
|
|
{
|
|
u8 D = (opc.hex >> 8) & 0x1;
|
|
u64 acc = dsp_get_long_acc(1 - D);
|
|
|
|
zeroWriteBackLog();
|
|
dsp_set_long_acc(D, acc);
|
|
|
|
Update_SR_Register64(acc);
|
|
}
|
|
|
|
// ADDAX $acD, $axS
|
|
// 0100 10sd xxxx xxxx
|
|
// Adds secondary accumulator $axS to accumulator register $acD.
|
|
void addax(const UDSPInstruction& opc)
|
|
{
|
|
u8 areg = (opc.hex >> 8) & 0x1;
|
|
u8 sreg = (opc.hex >> 9) & 0x1;
|
|
|
|
s64 ax = dsp_get_long_acx(sreg);
|
|
s64 acc = dsp_get_long_acc(areg);
|
|
acc += ax;
|
|
|
|
zeroWriteBackLog();
|
|
dsp_set_long_acc(areg, acc);
|
|
|
|
Update_SR_Register64(acc);
|
|
}
|
|
|
|
// ADDR $acD.M, $axS.L
|
|
// 0100 0ssd xxxx xxxx
|
|
// Adds register $axS.L to accumulator $acD.M register.
|
|
void addr(const UDSPInstruction& opc)
|
|
{
|
|
u8 areg = (opc.hex >> 8) & 0x1;
|
|
u8 sreg = ((opc.hex >> 9) & 0x3) + DSP_REG_AXL0;
|
|
|
|
s64 ax = (s16)g_dsp.r[sreg];
|
|
ax <<= 16;
|
|
|
|
s64 acc = dsp_get_long_acc(areg);
|
|
acc += ax;
|
|
|
|
zeroWriteBackLog();
|
|
dsp_set_long_acc(areg, acc);
|
|
|
|
Update_SR_Register64(acc);
|
|
}
|
|
|
|
// SUBR $acD.M, $axS.L
|
|
// 0101 0ssd xxxx xxxx
|
|
// Subtracts register $axS.L from accumulator $acD.M register.
|
|
void subr(const UDSPInstruction& opc)
|
|
{
|
|
u8 areg = (opc.hex >> 8) & 0x1;
|
|
u8 sreg = ((opc.hex >> 9) & 0x3) + DSP_REG_AXL0;
|
|
|
|
s64 ax = (s16)g_dsp.r[sreg];
|
|
ax <<= 16;
|
|
|
|
s64 acc = dsp_get_long_acc(areg);
|
|
acc -= ax;
|
|
|
|
zeroWriteBackLog();
|
|
dsp_set_long_acc(areg, acc);
|
|
|
|
Update_SR_Register64(acc);
|
|
}
|
|
|
|
// SUBAX $acD, $axS
|
|
// 0101 10sd xxxx xxxx
|
|
// Subtracts secondary accumulator $axS from accumulator register $acD.
|
|
void subax(const UDSPInstruction& opc)
|
|
{
|
|
int regD = (opc.hex >> 8) & 0x1;
|
|
int regS = (opc.hex >> 9) & 0x1;
|
|
|
|
s64 acc = dsp_get_long_acc(regD) - dsp_get_long_acx(regS);
|
|
|
|
zeroWriteBackLog();
|
|
dsp_set_long_acc(regD, acc);
|
|
Update_SR_Register64(acc);
|
|
}
|
|
|
|
// ADDIS $acD, #I
|
|
// 0000 010d iiii iiii
|
|
// Adds short immediate (8-bit sign extended) to mid accumulator $acD.hm.
|
|
void addis(const UDSPInstruction& opc)
|
|
{
|
|
u8 areg = (opc.hex >> 8) & 0x1;
|
|
|
|
s64 Imm = (s8)(u8)opc.hex;
|
|
Imm <<= 16;
|
|
s64 acc = dsp_get_long_acc(areg);
|
|
acc += Imm;
|
|
|
|
dsp_set_long_acc(areg, acc);
|
|
|
|
Update_SR_Register64(acc);
|
|
}
|
|
|
|
// ADDI $amR, #I
|
|
// 0000 001r 0000 0000
|
|
// iiii iiii iiii iiii
|
|
// Adds immediate (16-bit sign extended) to mid accumulator $acD.hm.
|
|
void addi(const UDSPInstruction& opc)
|
|
{
|
|
u8 areg = (opc.hex >> 8) & 0x1;
|
|
|
|
s64 sub = (s16)dsp_fetch_code();
|
|
sub <<= 16;
|
|
s64 acc = dsp_get_long_acc(areg);
|
|
acc += sub;
|
|
|
|
dsp_set_long_acc(areg, acc);
|
|
|
|
Update_SR_Register64(acc);
|
|
}
|
|
|
|
// LSL16 $acR
|
|
// 1111 000r xxxx xxxx
|
|
// Logically shifts left accumulator $acR by 16.
|
|
void lsl16(const UDSPInstruction& opc)
|
|
{
|
|
u8 areg = (opc.hex >> 8) & 0x1;
|
|
|
|
s64 acc = dsp_get_long_acc(areg);
|
|
acc <<= 16;
|
|
|
|
zeroWriteBackLog();
|
|
dsp_set_long_acc(areg, acc);
|
|
Update_SR_Register64(acc);
|
|
}
|
|
|
|
// LSR16 $acR
|
|
// 1111 010r xxxx xxxx
|
|
// Logically shifts right accumulator $acR by 16.
|
|
void lsr16(const UDSPInstruction& opc)
|
|
{
|
|
u8 areg = (opc.hex >> 8) & 0x1;
|
|
|
|
u64 acc = dsp_get_long_acc(areg);
|
|
|
|
acc >>= 16;
|
|
|
|
zeroWriteBackLog();
|
|
dsp_set_long_acc(areg, acc);
|
|
Update_SR_Register64(acc);
|
|
}
|
|
|
|
// ASR16 $acR
|
|
// 1001 r001 xxxx xxxx
|
|
// Arithmetically shifts right accumulator $acR by 16.
|
|
void asr16(const UDSPInstruction& opc)
|
|
{
|
|
u8 areg = (opc.hex >> 11) & 0x1;
|
|
|
|
s64 acc = dsp_get_long_acc(areg);
|
|
|
|
acc >>= 16;
|
|
|
|
zeroWriteBackLog();
|
|
dsp_set_long_acc(areg, acc);
|
|
|
|
Update_SR_Register64(acc);
|
|
}
|
|
|
|
// LSL $acR, #I
|
|
// 0001 010r 00ii iiii
|
|
// Logically shifts left accumulator $acR by number specified by value I.
|
|
void lsl(const UDSPInstruction& opc)
|
|
{
|
|
u16 shift = opc.ushift;
|
|
u64 acc = dsp_get_long_acc(opc.areg);
|
|
|
|
acc <<= shift;
|
|
|
|
dsp_set_long_acc(opc.areg, acc);
|
|
Update_SR_Register64(acc);
|
|
}
|
|
|
|
// LSR $acR, #I
|
|
// 0001 010r 01ii iiii
|
|
// Logically shifts left accumulator $acR by number specified by value
|
|
// calculated by negating sign extended bits 0-6.
|
|
void lsr(const UDSPInstruction& opc)
|
|
{
|
|
u16 shift = (u16) -(((s8)(opc.ushift << 2)) >> 2);
|
|
u64 acc = dsp_get_long_acc(opc.areg);
|
|
// Lop off the extraneous sign extension our 64-bit fake accum causes
|
|
acc &= 0x000000FFFFFFFFFFULL;
|
|
acc >>= shift;
|
|
|
|
dsp_set_long_acc(opc.areg, (s64)acc);
|
|
Update_SR_Register64(acc);
|
|
}
|
|
|
|
// ASL $acR, #I
|
|
// 0001 010r 10ii iiii
|
|
// Logically shifts left accumulator $acR by number specified by value I.
|
|
void asl(const UDSPInstruction& opc)
|
|
{
|
|
u16 shift = opc.ushift;
|
|
|
|
// arithmetic shift
|
|
u64 acc = dsp_get_long_acc(opc.areg);
|
|
acc <<= shift;
|
|
|
|
dsp_set_long_acc(opc.areg, acc);
|
|
|
|
Update_SR_Register64(acc);
|
|
}
|
|
|
|
// ASR $acR, #I
|
|
// 0001 010r 11ii iiii
|
|
// Arithmetically shifts right accumulator $acR by number specified by
|
|
// value calculated by negating sign extended bits 0-6.
|
|
void asr(const UDSPInstruction& opc)
|
|
{
|
|
u16 shift = (u16) -(((s8)(opc.ushift << 2)) >> 2);
|
|
|
|
// arithmetic shift
|
|
s64 acc = dsp_get_long_acc(opc.areg);
|
|
acc >>= shift;
|
|
|
|
dsp_set_long_acc(opc.areg, acc);
|
|
|
|
Update_SR_Register64(acc);
|
|
}
|
|
|
|
|
|
// (NEW)
|
|
// LSRN (fixed parameters)
|
|
// 0000 0010 1100 1010
|
|
// Logically shifts right accumulator $ACC0 by signed 16-bit value $AC1.M
|
|
// (if value negative, becomes left shift).
|
|
void lsrn(const UDSPInstruction& opc)
|
|
{
|
|
s16 shift = dsp_get_acc_m(1);
|
|
u64 acc = dsp_get_long_acc(0);
|
|
// Lop off the extraneous sign extension our 64-bit fake accum causes
|
|
acc &= 0x000000FFFFFFFFFFULL;
|
|
if (shift > 0) {
|
|
acc >>= shift;
|
|
} else if (shift < 0) {
|
|
acc <<= -shift;
|
|
}
|
|
dsp_set_long_acc(0, (s64)acc);
|
|
Update_SR_Register64(acc);
|
|
}
|
|
|
|
// (NEW)
|
|
// ASRN (fixed parameters)
|
|
// 0000 0010 1100 1011
|
|
// Arithmetically shifts right accumulator $ACC0 by signed 16-bit value $AC1.M
|
|
// (if value negative, becomes left shift).
|
|
void asrn(const UDSPInstruction& opc)
|
|
{
|
|
s16 shift = dsp_get_acc_m(1);
|
|
s64 acc = dsp_get_long_acc(0);
|
|
if (shift > 0) {
|
|
acc >>= shift;
|
|
} else if (shift < 0) {
|
|
acc <<= -shift;
|
|
}
|
|
dsp_set_long_acc(0, acc);
|
|
Update_SR_Register64(acc);
|
|
}
|
|
|
|
// LSRNRX
|
|
// 0011 01sd 1xxx xxxx
|
|
// 0011 10sd 1xxx xxxx
|
|
// Logically shifts right accumulator $ACC[D] by signed 16-bit value $AX[S].H
|
|
// Not described by Duddie's doc.
|
|
// x = extension (7 bits!!)
|
|
void lsrnrx(const UDSPInstruction& opc)
|
|
{
|
|
u8 dreg = (opc.hex >> 8) & 0x1; //accD
|
|
u8 sreg = (opc.hex >> 9) & 0x1; //axhS
|
|
u64 acc = dsp_get_long_acc(dreg);
|
|
s16 shift = g_dsp.r[DSP_REG_AXH0 + sreg];
|
|
acc &= 0x000000FFFFFFFFFFULL;
|
|
if (shift > 0) {
|
|
acc <<= shift;
|
|
} else if (shift < 0) {
|
|
acc >>= -shift;
|
|
}
|
|
|
|
zeroWriteBackLog();
|
|
|
|
dsp_set_long_acc(dreg, acc);
|
|
Update_SR_Register64(acc);
|
|
}
|
|
|
|
// LSRNR $acR
|
|
// 0011 11?d 1xxx xxxx
|
|
// Logically shifts right accumulator $ACC[D] by signed 16-bit value $AC[1-D].M
|
|
// Not described by Duddie's doc - at least not as a separate instruction.
|
|
// x = extension (7 bits!!)
|
|
void lsrnr(const UDSPInstruction& opc)
|
|
{
|
|
u8 D = (opc.hex >> 8) & 0x1;
|
|
s16 shift = dsp_get_acc_m(1-D);
|
|
u64 acc = dsp_get_long_acc(D);
|
|
acc &= 0x000000FFFFFFFFFFULL;
|
|
if (shift > 0) {
|
|
acc <<= shift;
|
|
} else if (shift < 0) {
|
|
acc >>= -shift;
|
|
}
|
|
|
|
zeroWriteBackLog();
|
|
|
|
dsp_set_long_acc(D, acc);
|
|
Update_SR_Register64(acc);
|
|
}
|
|
|
|
// CMPAR $acS axR.h
|
|
// 1100 0001 xxxx xxxx
|
|
// Compares accumulator $acS with accumulator axR.h.
|
|
// Not described by Duddie's doc - at least not as a separate instruction.
|
|
void cmpar(const UDSPInstruction& opc)
|
|
{
|
|
u8 rreg = ((opc.hex >> 12) & 0x1) + DSP_REG_AXH0;
|
|
u8 sreg = (opc.hex >> 11) & 0x1;
|
|
|
|
// we compare
|
|
s64 rr = (s16)g_dsp.r[rreg];
|
|
rr <<= 16;
|
|
|
|
s64 sr = dsp_get_long_acc(sreg);
|
|
|
|
Update_SR_Register64(sr - rr);
|
|
zeroWriteBackLog();
|
|
}
|
|
|
|
|
|
// CMP
|
|
// 1000 0010 xxxx xxxx
|
|
// Compares accumulator $ac0 with accumulator $ac1.
|
|
void cmp(const UDSPInstruction& opc)
|
|
{
|
|
s64 acc0 = dsp_get_long_acc(0);
|
|
s64 acc1 = dsp_get_long_acc(1);
|
|
|
|
Update_SR_Register64(acc0 - acc1);
|
|
zeroWriteBackLog();
|
|
}
|
|
|
|
// TST
|
|
// 1011 r001 xxxx xxxx
|
|
// Test accumulator %acR.
|
|
void tst(const UDSPInstruction& opc)
|
|
{
|
|
s8 reg = (opc.hex >> 11) & 0x1;
|
|
s64 acc = dsp_get_long_acc(reg);
|
|
|
|
Update_SR_Register64(acc);
|
|
zeroWriteBackLog();
|
|
}
|
|
|
|
} // namespace
|
|
|