349 lines
8.5 KiB
C++
349 lines
8.5 KiB
C++
// Copyright 2008 Dolphin Emulator Project
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// Copyright 2004 Duddie & Tratax
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// Licensed under GPLv2+
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// Refer to the license.txt file included.
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#include "Common/CommonFuncs.h"
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#include "Common/CPUDetect.h"
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#include "Common/Intrinsics.h"
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#include "Common/MemoryUtil.h"
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#include "Common/Thread.h"
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#include "Core/DSP/DSPAccelerator.h"
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#include "Core/DSP/DSPAnalyzer.h"
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#include "Core/DSP/DSPCore.h"
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#include "Core/DSP/DSPHost.h"
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#include "Core/DSP/DSPHWInterface.h"
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#include "Core/DSP/DSPInterpreter.h"
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#include "Core/DSP/DSPTables.h"
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static void gdsp_do_dma();
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void gdsp_ifx_init()
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{
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for (int i = 0; i < 256; i++)
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{
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g_dsp.ifx_regs[i] = 0;
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}
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g_dsp.mbox[0].store(0);
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g_dsp.mbox[1].store(0);
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}
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u32 gdsp_mbox_peek(u8 mbx)
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{
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return g_dsp.mbox[mbx].load();
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}
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void gdsp_mbox_write_h(u8 mbx, u16 val)
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{
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const u32 old_value = g_dsp.mbox[mbx].load(std::memory_order_acquire);
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const u32 new_value = (old_value & 0xffff) | (val << 16);
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g_dsp.mbox[mbx].store(new_value & ~0x80000000, std::memory_order_release);
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}
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void gdsp_mbox_write_l(u8 mbx, u16 val)
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{
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const u32 old_value = g_dsp.mbox[mbx].load(std::memory_order_acquire);
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const u32 new_value = (old_value & ~0xffff) | val;
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g_dsp.mbox[mbx].store(new_value | 0x80000000, std::memory_order_release);
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#if defined(_DEBUG) || defined(DEBUGFAST)
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if (mbx == GDSP_MBOX_DSP)
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{
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INFO_LOG(DSP_MAIL, "DSP(WM) B:%i M:0x%08x (pc=0x%04x)", mbx, gdsp_mbox_peek(GDSP_MBOX_DSP), g_dsp.pc);
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} else {
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INFO_LOG(DSP_MAIL, "CPU(WM) B:%i M:0x%08x (pc=0x%04x)", mbx, gdsp_mbox_peek(GDSP_MBOX_CPU), g_dsp.pc);
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}
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#endif
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}
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u16 gdsp_mbox_read_h(u8 mbx)
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{
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if (init_hax && mbx)
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{
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return 0x8054;
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}
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return (u16)(g_dsp.mbox[mbx].load() >> 16); // TODO: mask away the top bit?
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}
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u16 gdsp_mbox_read_l(u8 mbx)
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{
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const u32 value = g_dsp.mbox[mbx].load(std::memory_order_acquire);
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g_dsp.mbox[mbx].store(value & ~0x80000000, std::memory_order_release);
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if (init_hax && mbx)
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{
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init_hax = false;
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DSPCore_Reset();
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return 0x4348;
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}
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#if defined(_DEBUG) || defined(DEBUGFAST)
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if (mbx == GDSP_MBOX_DSP)
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{
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INFO_LOG(DSP_MAIL, "DSP(RM) B:%i M:0x%08x (pc=0x%04x)", mbx, gdsp_mbox_peek(GDSP_MBOX_DSP), g_dsp.pc);
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} else {
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INFO_LOG(DSP_MAIL, "CPU(RM) B:%i M:0x%08x (pc=0x%04x)", mbx, gdsp_mbox_peek(GDSP_MBOX_CPU), g_dsp.pc);
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}
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#endif
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return (u16)value;
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}
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void gdsp_ifx_write(u32 addr, u32 val)
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{
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g_dsp_cap->LogIFXWrite(addr, val);
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switch (addr & 0xff)
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{
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case DSP_DIRQ:
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if (val & 0x1)
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DSPHost::InterruptRequest();
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else
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INFO_LOG(DSPLLE, "Unknown Interrupt Request pc=%04x (%04x)", g_dsp.pc, val);
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break;
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case DSP_DMBH:
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gdsp_mbox_write_h(GDSP_MBOX_DSP, val);
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break;
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case DSP_DMBL:
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gdsp_mbox_write_l(GDSP_MBOX_DSP, val);
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break;
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case DSP_CMBH:
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return gdsp_mbox_write_h(GDSP_MBOX_CPU, val);
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case DSP_CMBL:
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return gdsp_mbox_write_l(GDSP_MBOX_CPU, val);
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case DSP_DSBL:
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g_dsp.ifx_regs[DSP_DSBL] = val;
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g_dsp.ifx_regs[DSP_DSCR] |= 4; // Doesn't really matter since we do DMA instantly
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if (!g_dsp.ifx_regs[DSP_AMDM])
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gdsp_do_dma();
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else
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NOTICE_LOG(DSPLLE, "Masked DMA skipped");
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g_dsp.ifx_regs[DSP_DSCR] &= ~4;
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g_dsp.ifx_regs[DSP_DSBL] = 0;
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break;
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case DSP_ACDATA1: // Accelerator write (Zelda type) - "UnkZelda"
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dsp_write_aram_d3(val);
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break;
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case DSP_GAIN:
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if (val)
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{
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INFO_LOG(DSPLLE,"Gain Written: 0x%04x", val);
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}
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case DSP_DSPA:
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case DSP_DSMAH:
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case DSP_DSMAL:
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case DSP_DSCR:
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g_dsp.ifx_regs[addr & 0xFF] = val;
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break;
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/*
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case DSP_ACCAL:
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dsp_step_accelerator();
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break;
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*/
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default:
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if ((addr & 0xff) >= 0xa0)
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{
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if (pdlabels[(addr & 0xFF) - 0xa0].name && pdlabels[(addr & 0xFF) - 0xa0].description)
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{
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INFO_LOG(DSPLLE, "%04x MW %s (%04x)", g_dsp.pc, pdlabels[(addr & 0xFF) - 0xa0].name, val);
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}
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else
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{
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ERROR_LOG(DSPLLE, "%04x MW %04x (%04x)", g_dsp.pc, addr, val);
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}
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}
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else
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{
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ERROR_LOG(DSPLLE, "%04x MW %04x (%04x)", g_dsp.pc, addr, val);
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}
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g_dsp.ifx_regs[addr & 0xFF] = val;
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break;
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}
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}
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static u16 _gdsp_ifx_read(u16 addr)
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{
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switch (addr & 0xff)
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{
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case DSP_DMBH:
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return gdsp_mbox_read_h(GDSP_MBOX_DSP);
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case DSP_DMBL:
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return gdsp_mbox_read_l(GDSP_MBOX_DSP);
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case DSP_CMBH:
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return gdsp_mbox_read_h(GDSP_MBOX_CPU);
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case DSP_CMBL:
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return gdsp_mbox_read_l(GDSP_MBOX_CPU);
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case DSP_DSCR:
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return g_dsp.ifx_regs[addr & 0xFF];
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case DSP_ACCELERATOR: // ADPCM Accelerator reads
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return dsp_read_accelerator();
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case DSP_ACDATA1: // Accelerator reads (Zelda type) - "UnkZelda"
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return dsp_read_aram_d3();
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default:
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if ((addr & 0xff) >= 0xa0)
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{
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if (pdlabels[(addr & 0xFF) - 0xa0].name && pdlabels[(addr & 0xFF) - 0xa0].description)
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{
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INFO_LOG(DSPLLE, "%04x MR %s (%04x)", g_dsp.pc, pdlabels[(addr & 0xFF) - 0xa0].name, g_dsp.ifx_regs[addr & 0xFF]);
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}
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else
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{
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ERROR_LOG(DSPLLE, "%04x MR %04x (%04x)", g_dsp.pc, addr, g_dsp.ifx_regs[addr & 0xFF]);
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}
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}
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else
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{
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ERROR_LOG(DSPLLE, "%04x MR %04x (%04x)", g_dsp.pc, addr, g_dsp.ifx_regs[addr & 0xFF]);
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}
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return g_dsp.ifx_regs[addr & 0xFF];
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}
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}
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u16 gdsp_ifx_read(u16 addr)
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{
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u16 retval = _gdsp_ifx_read(addr);
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g_dsp_cap->LogIFXRead(addr, retval);
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return retval;
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}
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static const u8* gdsp_idma_in(u16 dsp_addr, u32 addr, u32 size)
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{
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UnWriteProtectMemory(g_dsp.iram, DSP_IRAM_BYTE_SIZE, false);
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u8* dst = ((u8*)g_dsp.iram);
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for (u32 i = 0; i < size; i += 2)
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{
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*(u16*)&dst[dsp_addr + i] = Common::swap16(*(const u16*)&g_dsp.cpu_ram[(addr + i) & 0x0fffffff]);
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}
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WriteProtectMemory(g_dsp.iram, DSP_IRAM_BYTE_SIZE, false);
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DSPHost::CodeLoaded((const u8*)g_dsp.iram + dsp_addr, size);
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NOTICE_LOG(DSPLLE, "*** Copy new UCode from 0x%08x to 0x%04x (crc: %8x)", addr, dsp_addr, g_dsp.iram_crc);
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return dst + dsp_addr;
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}
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static const u8* gdsp_idma_out(u16 dsp_addr, u32 addr, u32 size)
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{
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ERROR_LOG(DSPLLE, "*** idma_out IRAM_DSP (0x%04x) -> RAM (0x%08x) : size (0x%08x)", dsp_addr / 2, addr, size);
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return nullptr;
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}
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#if _M_SSE >= 0x301
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static const __m128i s_mask = _mm_set_epi32(0x0E0F0C0DL, 0x0A0B0809L, 0x06070405L, 0x02030001L);
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#endif
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// TODO: These should eat clock cycles.
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static const u8* gdsp_ddma_in(u16 dsp_addr, u32 addr, u32 size)
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{
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u8* dst = ((u8*)g_dsp.dram);
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#if _M_SSE >= 0x301
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if (cpu_info.bSSSE3 && !(size % 16))
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{
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for (u32 i = 0; i < size; i += 16)
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{
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_mm_storeu_si128((__m128i *)&dst[dsp_addr + i], _mm_shuffle_epi8(_mm_loadu_si128((__m128i *)&g_dsp.cpu_ram[(addr + i) & 0x7FFFFFFF]), s_mask));
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}
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}
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else
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#endif
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{
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for (u32 i = 0; i < size; i += 2)
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{
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*(u16*)&dst[dsp_addr + i] = Common::swap16(*(const u16*)&g_dsp.cpu_ram[(addr + i) & 0x7FFFFFFF]);
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}
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}
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INFO_LOG(DSPLLE, "*** ddma_in RAM (0x%08x) -> DRAM_DSP (0x%04x) : size (0x%08x)", addr, dsp_addr / 2, size);
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return dst + dsp_addr;
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}
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static const u8* gdsp_ddma_out(u16 dsp_addr, u32 addr, u32 size)
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{
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const u8* src = ((const u8*)g_dsp.dram);
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#if _M_SSE >= 0x301
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if (cpu_info.bSSSE3 && !(size % 16))
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{
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for (u32 i = 0; i < size; i += 16)
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{
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_mm_storeu_si128((__m128i *)&g_dsp.cpu_ram[(addr + i) & 0x7FFFFFFF], _mm_shuffle_epi8(_mm_loadu_si128((__m128i *)&src[dsp_addr + i]), s_mask));
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}
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}
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else
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#endif
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{
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for (u32 i = 0; i < size; i += 2)
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{
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*(u16*)&g_dsp.cpu_ram[(addr + i) & 0x7FFFFFFF] = Common::swap16(*(const u16*)&src[dsp_addr + i]);
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}
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}
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INFO_LOG(DSPLLE, "*** ddma_out DRAM_DSP (0x%04x) -> RAM (0x%08x) : size (0x%08x)", dsp_addr / 2, addr, size);
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return src + dsp_addr;
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}
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static void gdsp_do_dma()
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{
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u32 addr = (g_dsp.ifx_regs[DSP_DSMAH] << 16) | g_dsp.ifx_regs[DSP_DSMAL];
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u16 ctl = g_dsp.ifx_regs[DSP_DSCR];
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u16 dsp_addr = g_dsp.ifx_regs[DSP_DSPA] * 2;
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u16 len = g_dsp.ifx_regs[DSP_DSBL];
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if (len > 0x4000)
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{
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ERROR_LOG(DSPLLE, "DMA ERROR: PC: %04x, Control: %04x, Address: %08x, DSP Address: %04x, Size: %04x", g_dsp.pc, ctl, addr, dsp_addr, len);
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exit(0);
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}
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#if defined(_DEBUG) || defined(DEBUGFAST)
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DEBUG_LOG(DSPLLE, "DMA pc: %04x, Control: %04x, Address: %08x, DSP Address: %04x, Size: %04x", g_dsp.pc, ctl, addr, dsp_addr, len);
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#endif
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const u8* copied_data_ptr = nullptr;
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switch (ctl & 0x3)
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{
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case (DSP_CR_DMEM | DSP_CR_TO_CPU):
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copied_data_ptr = gdsp_ddma_out(dsp_addr, addr, len);
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break;
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case (DSP_CR_DMEM | DSP_CR_FROM_CPU):
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copied_data_ptr = gdsp_ddma_in(dsp_addr, addr, len);
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break;
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case (DSP_CR_IMEM | DSP_CR_TO_CPU):
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copied_data_ptr = gdsp_idma_out(dsp_addr, addr, len);
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break;
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case (DSP_CR_IMEM | DSP_CR_FROM_CPU):
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copied_data_ptr = gdsp_idma_in(dsp_addr, addr, len);
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break;
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}
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if (copied_data_ptr)
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g_dsp_cap->LogDMA(ctl, addr, dsp_addr, len, copied_data_ptr);
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}
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