339 lines
6.2 KiB
C
339 lines
6.2 KiB
C
#ifndef __ASM_H__
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#define __ASM_H__
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#ifdef _LANGUAGE_ASSEMBLY
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/* Condition Register Bit Fields */
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#define cr0 0
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#define cr1 1
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#define cr2 2
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#define cr3 3
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#define cr4 4
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#define cr5 5
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#define cr6 6
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#define cr7 7
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/* General Purpose Registers (GPRs) */
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#define r0 0
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#define r1 1
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#define sp 1
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#define r2 2
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#define toc 2
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#define r3 3
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#define r4 4
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#define r5 5
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#define r6 6
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#define r7 7
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#define r8 8
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#define r9 9
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#define r10 10
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#define r11 11
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#define r12 12
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#define r13 13
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#define r14 14
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#define r15 15
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#define r16 16
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#define r17 17
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#define r18 18
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#define r19 19
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#define r20 20
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#define r21 21
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#define r22 22
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#define r23 23
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#define r24 24
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#define r25 25
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#define r26 26
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#define r27 27
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#define r28 28
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#define r29 29
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#define r30 30
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#define r31 31
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/* Floating Point Registers (FPRs) */
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#define fr0 0
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#define fr1 1
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#define fr2 2
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#define fr3 3
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#define fr4 4
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#define fr5 5
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#define fr6 6
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#define fr7 7
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#define fr8 8
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#define fr9 9
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#define fr10 10
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#define fr11 11
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#define fr12 12
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#define fr13 13
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#define fr14 14
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#define fr15 15
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#define fr16 16
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#define fr17 17
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#define fr18 18
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#define fr19 19
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#define fr20 20
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#define fr21 21
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#define fr22 22
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#define fr23 23
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#define fr24 24
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#define fr25 25
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#define fr26 26
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#define fr27 27
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#define fr28 28
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#define fr29 29
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#define fr30 30
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#define fr31 31
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#define vr0 0
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#define vr1 1
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#define vr2 2
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#define vr3 3
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#define vr4 4
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#define vr5 5
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#define vr6 6
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#define vr7 7
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#define vr8 8
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#define vr9 9
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#define vr10 10
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#define vr11 11
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#define vr12 12
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#define vr13 13
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#define vr14 14
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#define vr15 15
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#define vr16 16
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#define vr17 17
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#define vr18 18
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#define vr19 19
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#define vr20 20
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#define vr21 21
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#define vr22 22
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#define vr23 23
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#define vr24 24
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#define vr25 25
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#define vr26 26
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#define vr27 27
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#define vr28 28
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#define vr29 29
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#define vr30 30
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#define vr31 31
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#endif //_LANGUAGE_ASSEMBLY
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#define SPRG0 272
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#define SPRG1 273
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#define SPRG2 274
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#define SPRG3 275
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#define PMC1 953
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#define PMC2 954
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#define PMC3 957
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#define PMC4 958
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#define MMCR0 952
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#define MMCR1 956
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#define LINK_REGISTER_CALLEE_UPDATE_ROOM 4
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#define EXCEPTION_NUMBER 8
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#define SRR0_OFFSET 12
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#define SRR1_OFFSET 16
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#define GPR0_OFFSET 20
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#define GPR1_OFFSET 24
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#define GPR2_OFFSET 28
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#define GPR3_OFFSET 32
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#define GPR4_OFFSET 36
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#define GPR5_OFFSET 40
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#define GPR6_OFFSET 44
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#define GPR7_OFFSET 48
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#define GPR8_OFFSET 52
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#define GPR9_OFFSET 56
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#define GPR10_OFFSET 60
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#define GPR11_OFFSET 64
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#define GPR12_OFFSET 68
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#define GPR13_OFFSET 72
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#define GPR14_OFFSET 76
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#define GPR15_OFFSET 80
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#define GPR16_OFFSET 84
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#define GPR17_OFFSET 88
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#define GPR18_OFFSET 92
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#define GPR19_OFFSET 96
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#define GPR20_OFFSET 100
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#define GPR21_OFFSET 104
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#define GPR22_OFFSET 108
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#define GPR23_OFFSET 112
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#define GPR24_OFFSET 116
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#define GPR25_OFFSET 120
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#define GPR26_OFFSET 124
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#define GPR27_OFFSET 128
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#define GPR28_OFFSET 132
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#define GPR29_OFFSET 136
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#define GPR30_OFFSET 140
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#define GPR31_OFFSET 144
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#define GQR0_OFFSET 148
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#define GQR1_OFFSET 152
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#define GQR2_OFFSET 156
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#define GQR3_OFFSET 160
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#define GQR4_OFFSET 164
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#define GQR5_OFFSET 168
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#define GQR6_OFFSET 172
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#define GQR7_OFFSET 176
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#define CR_OFFSET 180
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#define LR_OFFSET 184
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#define CTR_OFFSET 188
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#define XER_OFFSET 192
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#define MSR_OFFSET 196
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#define DAR_OFFSET 200
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#define STATE_OFFSET 204
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#define MODE_OFFSET 206
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#define FPR0_OFFSET 208
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#define FPR1_OFFSET 216
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#define FPR2_OFFSET 224
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#define FPR3_OFFSET 232
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#define FPR4_OFFSET 240
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#define FPR5_OFFSET 248
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#define FPR6_OFFSET 256
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#define FPR7_OFFSET 264
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#define FPR8_OFFSET 272
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#define FPR9_OFFSET 280
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#define FPR10_OFFSET 288
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#define FPR11_OFFSET 296
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#define FPR12_OFFSET 304
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#define FPR13_OFFSET 312
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#define FPR14_OFFSET 320
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#define FPR15_OFFSET 328
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#define FPR16_OFFSET 336
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#define FPR17_OFFSET 344
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#define FPR18_OFFSET 352
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#define FPR19_OFFSET 360
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#define FPR20_OFFSET 368
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#define FPR21_OFFSET 376
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#define FPR22_OFFSET 384
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#define FPR23_OFFSET 392
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#define FPR24_OFFSET 400
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#define FPR25_OFFSET 408
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#define FPR26_OFFSET 416
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#define FPR27_OFFSET 424
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#define FPR28_OFFSET 432
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#define FPR29_OFFSET 440
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#define FPR30_OFFSET 448
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#define FPR31_OFFSET 456
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#define FPSCR_OFFSET 464
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#define PSR0_OFFSET 472
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#define PSR1_OFFSET 480
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#define PSR2_OFFSET 488
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#define PSR3_OFFSET 496
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#define PSR4_OFFSET 504
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#define PSR5_OFFSET 512
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#define PSR6_OFFSET 520
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#define PSR7_OFFSET 528
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#define PSR8_OFFSET 536
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#define PSR9_OFFSET 544
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#define PSR10_OFFSET 552
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#define PSR11_OFFSET 560
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#define PSR12_OFFSET 568
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#define PSR13_OFFSET 576
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#define PSR14_OFFSET 584
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#define PSR15_OFFSET 592
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#define PSR16_OFFSET 600
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#define PSR17_OFFSET 608
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#define PSR18_OFFSET 616
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#define PSR19_OFFSET 624
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#define PSR20_OFFSET 632
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#define PSR21_OFFSET 640
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#define PSR22_OFFSET 648
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#define PSR23_OFFSET 656
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#define PSR24_OFFSET 664
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#define PSR25_OFFSET 672
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#define PSR26_OFFSET 680
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#define PSR27_OFFSET 688
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#define PSR28_OFFSET 696
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#define PSR29_OFFSET 704
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#define PSR30_OFFSET 712
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#define PSR31_OFFSET 720
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/*
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* maintain the EABI requested 8 bytes aligment
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* As SVR4 ABI requires 16, make it 16 (as some
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* exception may need more registers to be processed...)
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*/
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#define EXCEPTION_FRAME_END 728
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#define IBAT0U 528
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#define IBAT0L 529
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#define IBAT1U 530
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#define IBAT1L 531
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#define IBAT2U 532
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#define IBAT2L 533
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#define IBAT3U 534
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#define IBAT3L 535
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#define IBAT4U 560
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#define IBAT4L 561
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#define IBAT5U 562
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#define IBAT5L 563
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#define IBAT6U 564
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#define IBAT6L 565
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#define IBAT7U 566
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#define IBAT7L 567
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#define DBAT0U 536
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#define DBAT0L 537
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#define DBAT1U 538
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#define DBAT1L 539
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#define DBAT2U 540
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#define DBAT2L 541
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#define DBAT3U 542
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#define DBAT3L 543
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#define DBAT4U 568
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#define DBAT4L 569
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#define DBAT5U 570
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#define DBAT5L 571
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#define DBAT6U 572
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#define DBAT6L 573
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#define DBAT7U 574
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#define DBAT7L 575
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#define HID0 1008
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#define HID1 1009
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#define HID2 920
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#define HID4 1011
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#define GQR0 912
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#define GQR1 913
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#define GQR2 914
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#define GQR3 915
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#define GQR4 916
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#define GQR5 917
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#define GQR6 918
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#define GQR7 919
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#define L2CR 1017
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#define WPAR 921
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#define DMAU 922
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#define DMAL 923
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#define MSR_RI 0x00000002
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#define MSR_DR 0x00000010
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#define MSR_IR 0x00000020
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#define MSR_IP 0x00000040
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#define MSR_SE 0x00000400
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#define MSR_ME 0x00001000
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#define MSR_FP 0x00002000
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#define MSR_POW 0x00004000
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#define MSR_EE 0x00008000
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#define PPC_ALIGNMENT 8
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#define PPC_CACHE_ALIGNMENT 32
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#endif //__ASM_H__
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