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JitArm64: divwx - Optimize comparisons to 0x80000000

This commit is contained in:
JosJuice 2021-08-21 20:28:18 +02:00
parent 91b112b984
commit feefc17b02
1 changed files with 4 additions and 14 deletions
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18
Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp
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@ -1384,15 +1384,9 @@ void JitArm64::divwx(UGeckoInstruction inst)
} }
else if (divisor == -1) else if (divisor == -1)
{ {
ARM64Reg WA = gpr.GetReg();
// Rd = (Ra == 0x80000000) ? 0xFFFFFFFF : -Ra // Rd = (Ra == 0x80000000) ? 0xFFFFFFFF : -Ra
MOVI2R(WA, 0x80000000); NEGS(gpr.R(d), gpr.R(a));
CMP(gpr.R(a), WA); CSINV(gpr.R(d), gpr.R(d), ARM64Reg::WZR, CCFlags::CC_VC);
NEG(gpr.R(d), gpr.R(a));
CSINV(gpr.R(d), gpr.R(d), ARM64Reg::WZR, CCFlags::CC_NEQ);
gpr.Unlock(WA);
} }
else if (divisor == 2 || divisor == -2) else if (divisor == 2 || divisor == -2)
{ {
@ -1484,15 +1478,13 @@ void JitArm64::divwx(UGeckoInstruction inst)
gpr.BindToRegister(d, d == a || d == b); gpr.BindToRegister(d, d == a || d == b);
ARM64Reg WA = gpr.GetReg();
ARM64Reg RA = gpr.R(a); ARM64Reg RA = gpr.R(a);
ARM64Reg RB = gpr.R(b); ARM64Reg RB = gpr.R(b);
ARM64Reg RD = gpr.R(d); ARM64Reg RD = gpr.R(d);
FixupBranch overflow1 = CBZ(RB); FixupBranch overflow1 = CBZ(RB);
MOVI2R(WA, -0x80000000LL); NEGS(ARM64Reg::WZR, RA); // Is RA 0x80000000?
CMP(RA, WA); CCMN(RB, 1, 0, CC_VS); // Is RB -1?
CCMN(RB, 1, 0, CC_EQ);
FixupBranch overflow2 = B(CC_EQ); FixupBranch overflow2 = B(CC_EQ);
SDIV(RD, RA, RB); SDIV(RD, RA, RB);
FixupBranch done = B(); FixupBranch done = B();
@ -1504,8 +1496,6 @@ void JitArm64::divwx(UGeckoInstruction inst)
SetJumpTarget(done); SetJumpTarget(done);
gpr.Unlock(WA);
if (inst.Rc) if (inst.Rc)
ComputeRC0(RD); ComputeRC0(RD);
} }