Merge pull request #3195 from lioncash/android
Arm64Emitter: Minor changes
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commit
fe10a20be1
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@ -3,6 +3,7 @@
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// Refer to the license.txt file included.
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#include <algorithm>
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#include <cstring>
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#include <vector>
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#include "Common/Arm64Emitter.h"
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@ -312,6 +313,12 @@ const u8* ARM64XEmitter::AlignCodePage()
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return m_code;
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}
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void ARM64XEmitter::Write32(u32 value)
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{
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std::memcpy(m_code, &value, sizeof(u32));
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m_code += sizeof(u32);
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}
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void ARM64XEmitter::FlushIcache()
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{
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FlushIcacheSection(m_lastCacheFlushEnd, m_code);
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@ -815,32 +822,32 @@ void ARM64XEmitter::EncodeLoadStoreUnscaled(u32 size, u32 op, ARM64Reg Rt, ARM64
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Write32((size << 30) | (0b111 << 27) | (op << 22) | ((imm & 0x1FF) << 12) | (Rn << 5) | Rt);
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}
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static inline bool IsInRangeImm19(s64 distance)
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static constexpr bool IsInRangeImm19(s64 distance)
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{
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return (distance >= -0x40000 && distance <= 0x3FFFF);
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}
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static inline bool IsInRangeImm14(s64 distance)
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static constexpr bool IsInRangeImm14(s64 distance)
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{
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return (distance >= -0x2000 && distance <= 0x1FFF);
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}
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static inline bool IsInRangeImm26(s64 distance)
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static constexpr bool IsInRangeImm26(s64 distance)
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{
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return (distance >= -0x2000000 && distance <= 0x1FFFFFF);
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}
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static inline u32 MaskImm19(s64 distance)
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static constexpr u32 MaskImm19(s64 distance)
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{
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return distance & 0x7FFFF;
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}
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static inline u32 MaskImm14(s64 distance)
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static constexpr u32 MaskImm14(s64 distance)
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{
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return distance & 0x3FFF;
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}
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static inline u32 MaskImm26(s64 distance)
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static constexpr u32 MaskImm26(s64 distance)
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{
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return distance & 0x3FFFFFF;
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}
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@ -81,19 +81,19 @@ enum ARM64Reg
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INVALID_REG = 0xFFFFFFFF
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};
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inline bool Is64Bit(ARM64Reg reg) { return (reg & 0x20) != 0; }
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inline bool IsSingle(ARM64Reg reg) { return (reg & 0xC0) == 0x40; }
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inline bool IsDouble(ARM64Reg reg) { return (reg & 0xC0) == 0x80; }
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inline bool IsScalar(ARM64Reg reg) { return IsSingle(reg) || IsDouble(reg); }
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inline bool IsQuad(ARM64Reg reg) { return (reg & 0xC0) == 0xC0; }
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inline bool IsVector(ARM64Reg reg) { return (reg & 0xC0) != 0; }
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inline bool IsGPR(ARM64Reg reg) { return (int)reg < 0x40; }
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constexpr bool Is64Bit(ARM64Reg reg) { return (reg & 0x20) != 0; }
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constexpr bool IsSingle(ARM64Reg reg) { return (reg & 0xC0) == 0x40; }
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constexpr bool IsDouble(ARM64Reg reg) { return (reg & 0xC0) == 0x80; }
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constexpr bool IsScalar(ARM64Reg reg) { return IsSingle(reg) || IsDouble(reg); }
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constexpr bool IsQuad(ARM64Reg reg) { return (reg & 0xC0) == 0xC0; }
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constexpr bool IsVector(ARM64Reg reg) { return (reg & 0xC0) != 0; }
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constexpr bool IsGPR(ARM64Reg reg) { return static_cast<int>(reg) < 0x40; }
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inline ARM64Reg DecodeReg(ARM64Reg reg) { return (ARM64Reg)(reg & 0x1F); }
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inline ARM64Reg EncodeRegTo64(ARM64Reg reg) { return (ARM64Reg)(reg | 0x20); }
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inline ARM64Reg EncodeRegToSingle(ARM64Reg reg) { return (ARM64Reg)(DecodeReg(reg) + S0); }
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inline ARM64Reg EncodeRegToDouble(ARM64Reg reg) { return (ARM64Reg)((reg & ~0xC0) | 0x80); }
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inline ARM64Reg EncodeRegToQuad(ARM64Reg reg) { return (ARM64Reg)(reg | 0xC0); }
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constexpr ARM64Reg DecodeReg(ARM64Reg reg) { return static_cast<ARM64Reg>(reg & 0x1F); }
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constexpr ARM64Reg EncodeRegTo64(ARM64Reg reg) { return static_cast<ARM64Reg>(reg | 0x20); }
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constexpr ARM64Reg EncodeRegToSingle(ARM64Reg reg) { return static_cast<ARM64Reg>(DecodeReg(reg) + S0); }
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constexpr ARM64Reg EncodeRegToDouble(ARM64Reg reg) { return static_cast<ARM64Reg>((reg & ~0xC0) | 0x80); }
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constexpr ARM64Reg EncodeRegToQuad(ARM64Reg reg) { return static_cast<ARM64Reg>(reg | 0xC0); }
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// For AND/TST/ORR/EOR etc
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bool IsImmLogical(uint64_t value, unsigned int width, unsigned int *n, unsigned int *imm_s, unsigned int *imm_r);
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@ -359,11 +359,7 @@ private:
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void EncodeLoadStoreUnscaled(u32 size, u32 op, ARM64Reg Rt, ARM64Reg Rn, s32 imm);
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protected:
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inline void Write32(u32 value)
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{
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*(u32*)m_code = value;
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m_code += 4;
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}
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void Write32(u32 value);
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public:
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ARM64XEmitter()
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