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Merge pull request #9410 from lioncash/enum2 

Arm64Emitter: Convert ArithOption enums into enum classes
This commit is contained in:
Léo Lam 2021-01-01 13:25:35 +01:00 committed by GitHub
parent 452aad29f1 95cc53edec
commit fcdcdd7beb
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GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 41 additions and 45 deletions
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6
Source/Core/Common/Arm64Emitter.cpp
View File

@ -572,8 +572,7 @@ void ARM64XEmitter::EncodeArithmeticInst(u32 instenc, bool flags, ARM64Reg Rd, A
Rn = DecodeReg(Rn);
Rm = DecodeReg(Rm);
Write32((b64Bit << 31) | (flags << 29) | (ArithEnc[instenc] << 21) |
(Option.GetType() == ArithOption::TYPE_EXTENDEDREG ? (1 << 21) : 0) | (Rm << 16) |
Option.GetData() | (Rn << 5) | Rd);
(Option.IsExtended() ? (1 << 21) : 0) | (Rm << 16) | Option.GetData() | (Rn << 5) | Rd);
}
void ARM64XEmitter::EncodeArithmeticCarryInst(u32 op, bool flags, ARM64Reg Rd, ARM64Reg Rn,
@ -2617,8 +2616,7 @@ void ARM64FloatEmitter::EncodeLoadStorePair(u32 size, bool load, IndexType type,
void ARM64FloatEmitter::EncodeLoadStoreRegisterOffset(u32 size, bool load, ARM64Reg Rt, ARM64Reg Rn,
ArithOption Rm)
{
ASSERT_MSG(DYNA_REC, Rm.GetType() == ArithOption::TYPE_EXTENDEDREG,
"%s must contain an extended reg as Rm!", __func__);
ASSERT_MSG(DYNA_REC, Rm.IsExtended(), "%s must contain an extended reg as Rm!", __func__);
u32 encoded_size = 0;
u32 encoded_op = 0;

80
Source/Core/Common/Arm64Emitter.h
View File

@ -382,34 +382,33 @@ enum class BarrierType
class ArithOption
{
public:
enum WidthSpecifier
{
WIDTH_DEFAULT,
WIDTH_32BIT,
WIDTH_64BIT,
};
enum ExtendSpecifier
{
EXTEND_UXTB = 0x0,
EXTEND_UXTH = 0x1,
EXTEND_UXTW = 0x2, /* Also LSL on 32bit width */
EXTEND_UXTX = 0x3, /* Also LSL on 64bit width */
EXTEND_SXTB = 0x4,
EXTEND_SXTH = 0x5,
EXTEND_SXTW = 0x6,
EXTEND_SXTX = 0x7,
};
enum TypeSpecifier
{
TYPE_EXTENDEDREG,
TYPE_IMM,
TYPE_SHIFTEDREG,
};
private:
enum class WidthSpecifier
{
Default,
Width32Bit,
Width64Bit,
};
enum class ExtendSpecifier
{
UXTB = 0x0,
UXTH = 0x1,
UXTW = 0x2, /* Also LSL on 32bit width */
UXTX = 0x3, /* Also LSL on 64bit width */
SXTB = 0x4,
SXTH = 0x5,
SXTW = 0x6,
SXTX = 0x7,
};
enum class TypeSpecifier
{
ExtendedReg,
Immediate,
ShiftedReg,
};
ARM64Reg m_destReg;
WidthSpecifier m_width;
ExtendSpecifier m_extend;
@ -436,16 +435,16 @@ public:
m_shift = 0;
m_destReg = Rd;
m_type = TYPE_EXTENDEDREG;
m_type = TypeSpecifier::ExtendedReg;
if (Is64Bit(Rd))
{
m_width = WIDTH_64BIT;
m_extend = EXTEND_UXTX;
m_width = WidthSpecifier::Width64Bit;
m_extend = ExtendSpecifier::UXTX;
}
else
{
m_width = WIDTH_32BIT;
m_extend = EXTEND_UXTW;
m_width = WidthSpecifier::Width32Bit;
m_extend = ExtendSpecifier::UXTW;
}
m_shifttype = ST_LSL;
}
@ -454,38 +453,37 @@ public:
m_destReg = Rd;
m_shift = shift;
m_shifttype = shift_type;
m_type = TYPE_SHIFTEDREG;
m_type = TypeSpecifier::ShiftedReg;
if (Is64Bit(Rd))
{
m_width = WIDTH_64BIT;
m_width = WidthSpecifier::Width64Bit;
if (shift == 64)
m_shift = 0;
}
else
{
m_width = WIDTH_32BIT;
m_width = WidthSpecifier::Width32Bit;
if (shift == 32)
m_shift = 0;
}
}
TypeSpecifier GetType() const { return m_type; }
ARM64Reg GetReg() const { return m_destReg; }
u32 GetData() const
{
switch (m_type)
{
case TYPE_EXTENDEDREG:
return (m_extend << 13) | (m_shift << 10);
break;
case TYPE_SHIFTEDREG:
case TypeSpecifier::ExtendedReg:
return (static_cast<u32>(m_extend) << 13) | (m_shift << 10);
case TypeSpecifier::ShiftedReg:
return (m_shifttype << 22) | (m_shift << 10);
break;
default:
DEBUG_ASSERT_MSG(DYNA_REC, false, "Invalid type in GetData");
break;
}
return 0;
}
bool IsExtended() const { return m_type == TypeSpecifier::ExtendedReg; }
};
class ARM64XEmitter