add definitions of some bp mem bits relating to interlacing (no behavior change)
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@7683 8ced0084-cf51-0410-be5f-012b33b47a6e
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@ -239,6 +239,30 @@ void SetTextureMode(const BPCmd &bp)
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void SetInterlacingMode(const BPCmd &bp)
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{
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// TODO
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switch (bp.address)
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{
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case BPMEM_FIELDMODE:
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{
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// SDK always sets bpmem.lineptwidth.lineaspect via BPMEM_LINEPTWIDTH
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// just before this cmd
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const char *action[] = { "don't adjust", "adjust" };
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DEBUG_LOG(VIDEO, "BPMEM_FIELDMODE texLOD:%s lineaspect:%s",
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action[bpmem.fieldmode.texLOD],
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action[bpmem.lineptwidth.lineaspect]);
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}
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break;
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case BPMEM_FIELDMASK:
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{
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// Determines if fields will be written to EFB (always computed)
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const char *action[] = { "skip", "write" };
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DEBUG_LOG(VIDEO, "BPMEM_FIELDMASK even:%s odd:%s",
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action[bpmem.fieldmask.even], action[bpmem.fieldmask.odd]);
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}
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break;
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default:
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ERROR_LOG(VIDEO, "SetInterlacingMode default");
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break;
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}
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}
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};
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@ -592,7 +592,7 @@ union LPSize
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u32 pointsize : 8; // in 1/6th pixels
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u32 lineoff : 3;
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u32 pointoff : 3;
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u32 lineaspect : 1;
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u32 lineaspect : 1; // interlacing: adjust for pixels having AR of 1/2
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u32 padding : 1;
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};
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u32 hex;
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@ -748,6 +748,26 @@ union ConstantAlpha
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u32 hex;
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};
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union FieldMode
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{
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struct
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{
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u32 texLOD : 1; // adjust vert tex LOD computation to account for interlacing
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};
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u32 hex;
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};
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union FieldMask
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{
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struct
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{
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// If bit is not set, do not write field to EFB
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u32 odd : 1;
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u32 even : 1;
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};
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u32 hex;
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};
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#define PIXELFMT_RGB8_Z24 0
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#define PIXELFMT_RGBA6_Z24 1
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#define PIXELFMT_RGB565_Z16 2
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@ -910,7 +930,7 @@ struct BPMemory
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BlendMode blendmode; //41
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ConstantAlpha dstalpha; //42
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PE_CONTROL zcontrol; //43 GXSetZCompLoc, GXPixModeSync
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u32 fieldmask; //44
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FieldMask fieldmask; //44
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u32 drawdone; //45, bit1=1 if end of list
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u32 unknown5; //46 clock?
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u32 petoken; //47
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@ -936,7 +956,7 @@ struct BPMemory
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u32 tlutXferDest; //65
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u32 texinvalidate;//66
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u32 metric; //67
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u32 fieldmode;//68
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FieldMode fieldmode;//68
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u32 unknown10[7];//69-6F
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u32 unknown11[16];//70-7F
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FourTexUnits tex[2]; //80-bf
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