DSPLLE: Split SRS into SRS and SRSH
Hardware testing indicated that SRS uses a different list of registers than LRS (specifically, acS.h can be used with SRSH but not LRS, and SRS does not support AX registers, and there are 2 encodings that do nothing).
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Pokechu22
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@ -18,7 +18,7 @@
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namespace DSP
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{
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// clang-format off
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const std::array<DSPOPCTemplate, 214> s_opcodes =
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const std::array<DSPOPCTemplate, 215> s_opcodes =
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{{
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// # of parameters----+ {type, size, loc, lshift, mask} branch reads PC // instruction approximation
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// name opcode mask size-V V param 1 param 2 param 3 extendable uncond. updates SR
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@ -192,7 +192,8 @@ const std::array<DSPOPCTemplate, 214> s_opcodes =
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//2
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{"LRS", 0x2000, 0xf800, 1, 2, {{P_REG18, 1, 0, 8, 0x0700}, {P_MEM, 1, 0, 0, 0x00ff}}, false, false, false, false, false}, // $(D+24) = MEM[($cr[0-7] << 8) | I]
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{"SRS", 0x2800, 0xf800, 1, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_REG18, 1, 0, 8, 0x0700}}, false, false, false, false, false}, // MEM[($cr[0-7] << 8) | I] = $(S+24)
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{"SRSH", 0x2800, 0xfe00, 1, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_ACCH, 1, 0, 8, 0x0100}}, false, false, false, false, false}, // MEM[($cr[0-7] << 8) | I] = $acS.h
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{"SRS", 0x2c00, 0xfc00, 1, 2, {{P_MEM, 1, 0, 0, 0x00ff}, {P_REG1C, 1, 0, 8, 0x0300}}, false, false, false, false, false}, // MEM[($cr[0-7] << 8) | I] = $(S+24)
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// opcodes that can be extended
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@ -44,16 +44,13 @@ enum partype_t
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P_ACCM = P_REG | 0x1e00, // used for mid part of accum
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// The following are not in gcdsptool
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P_ACCM_D = P_REG | 0x1e80,
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P_ACC = P_REG | 0x2000, // used for full accum.
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P_ACC = P_REG | 0x2000, // used for full accum.
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P_ACCH = P_REG | 0x1000, // used for high part of accum
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P_ACC_D = P_REG | 0x2080,
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P_AX = P_REG | 0x2200,
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P_REGS_MASK = 0x03f80, // gcdsptool's value = 0x01f80
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P_REF = P_REG | 0x4000,
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P_PRG = P_REF | P_REG,
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// The following seem like junk:
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// P_REG10 = P_REG | 0x1000,
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// P_AX_D = P_REG | 0x2280,
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};
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struct param2_t
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@ -8,15 +8,29 @@
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namespace DSP::Interpreter
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{
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// SRS @M, $(0x18+S)
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// 0010 1sss mmmm mmmm
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// Move value from register $(0x18+S) to data memory pointed by address
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// SRSH @M, $acS.h
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// 0010 10ss mmmm mmmm
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// Move value from register $acS.h to data memory pointed by address
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// CR[0-7] | M. That is, the upper 8 bits of the address are the
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// bottom 8 bits from CR, and the lower 8 bits are from the 8-bit immediate.
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void Interpreter::srsh(const UDSPInstruction opc)
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{
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auto& state = m_dsp_core.DSPState();
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const auto reg = static_cast<u8>(((opc >> 8) & 0x1) + DSP_REG_ACH0);
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const auto addr = static_cast<u16>((state.r.cr << 8) | (opc & 0xFF));
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state.WriteDMEM(addr, OpReadRegister(reg));
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}
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// SRS @M, $(0x1C+S)
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// 0010 11ss mmmm mmmm
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// Move value from register $(0x1C+S) to data memory pointed by address
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// CR[0-7] | M. That is, the upper 8 bits of the address are the
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// bottom 8 bits from CR, and the lower 8 bits are from the 8-bit immediate.
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void Interpreter::srs(const UDSPInstruction opc)
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{
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auto& state = m_dsp_core.DSPState();
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const auto reg = static_cast<u8>(((opc >> 8) & 0x7) + 0x18);
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const auto reg = static_cast<u8>(((opc >> 8) & 0x3) + DSP_REG_ACL0);
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const auto addr = static_cast<u16>((state.r.cr << 8) | (opc & 0xFF));
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if (reg >= DSP_REG_ACM0)
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@ -19,7 +19,7 @@ struct InterpreterOpInfo
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};
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// clang-format off
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constexpr std::array<InterpreterOpInfo, 124> s_opcodes
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constexpr std::array<InterpreterOpInfo, 125> s_opcodes
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{{
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{0x0000, 0xfffc, &Interpreter::nop},
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@ -101,7 +101,8 @@ constexpr std::array<InterpreterOpInfo, 124> s_opcodes
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// 2
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{0x2000, 0xf800, &Interpreter::lrs},
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{0x2800, 0xf800, &Interpreter::srs},
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{0x2800, 0xfe00, &Interpreter::srsh},
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{0x2c00, 0xfc00, &Interpreter::srs},
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// opcodes that can be extended
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@ -149,6 +149,7 @@ public:
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void srri(UDSPInstruction opc);
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void srrn(UDSPInstruction opc);
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void srs(UDSPInstruction opc);
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void srsh(UDSPInstruction opc);
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void sub(UDSPInstruction opc);
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void subarn(UDSPInstruction opc);
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void subax(UDSPInstruction opc);
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@ -88,6 +88,7 @@ public:
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void bloopi(UDSPInstruction opc);
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// Load/Store
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void srsh(UDSPInstruction opc);
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void srs(UDSPInstruction opc);
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void lrs(UDSPInstruction opc);
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void lr(UDSPInstruction opc);
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@ -12,14 +12,35 @@ using namespace Gen;
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namespace DSP::JIT::x64
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{
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// SRS @M, $(0x18+S)
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// SRSH @M, $acS.h
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// 0010 1sss mmmm mmmm
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// Move value from register $(0x18+S) to data memory pointed by address
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// Move value from register $acS.h to data memory pointed by address
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// CR[0-7] | M. That is, the upper 8 bits of the address are the
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// bottom 8 bits from CR, and the lower 8 bits are from the 8-bit immediate.
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void DSPEmitter::srsh(const UDSPInstruction opc)
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{
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u8 reg = ((opc >> 8) & 0x1) + DSP_REG_ACH0;
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// u16 addr = (g_dsp.r.cr << 8) | (opc & 0xFF);
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X64Reg tmp1 = m_gpr.GetFreeXReg();
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dsp_op_read_reg(reg, tmp1, RegisterExtension::Zero);
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dsp_op_read_reg(DSP_REG_CR, RAX, RegisterExtension::Zero);
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SHL(16, R(EAX), Imm8(8));
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OR(16, R(EAX), Imm16(opc & 0xFF));
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dmem_write(tmp1);
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m_gpr.PutXReg(tmp1);
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}
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// SRS @M, $(0x1C+S)
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// 0010 1sss mmmm mmmm
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// Move value from register $(0x1C+S) to data memory pointed by address
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// CR[0-7] | M. That is, the upper 8 bits of the address are the
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// bottom 8 bits from CR, and the lower 8 bits are from the 8-bit immediate.
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void DSPEmitter::srs(const UDSPInstruction opc)
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{
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u8 reg = ((opc >> 8) & 0x7) + 0x18;
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u8 reg = ((opc >> 8) & 0x3) + DSP_REG_ACL0;
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// u16 addr = (g_dsp.r.cr << 8) | (opc & 0xFF);
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X64Reg tmp1 = m_gpr.GetFreeXReg();
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@ -19,7 +19,7 @@ struct JITOpInfo
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};
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// clang-format off
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const std::array<JITOpInfo, 124> s_opcodes =
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const std::array<JITOpInfo, 125> s_opcodes =
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{{
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{0x0000, 0xfffc, &DSPEmitter::nop},
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@ -101,7 +101,8 @@ const std::array<JITOpInfo, 124> s_opcodes =
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// 2
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{0x2000, 0xf800, &DSPEmitter::lrs},
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{0x2800, 0xf800, &DSPEmitter::srs},
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{0x2800, 0xfe00, &DSPEmitter::srsh},
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{0x2c00, 0xfc00, &DSPEmitter::srs},
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// opcodes that can be extended
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@ -0,0 +1,131 @@
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incdir "tests"
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include "dsp_base.inc"
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test_main:
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; Test registers used by LRS and SRS
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LRI $CR, #0x0000
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CALL clear_regs
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CALL store_mem_sr
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; Write with SR, read with LR
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LRI $AR0, #0xA00A
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CALL create_pattern
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CALL store_mem_sr
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CALL send_back
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CALL clear_regs
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CALL read_mem_lr
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CALL send_back
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; Write with SR, read with LRS
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LRI $AR0, #0xB00B
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CALL create_pattern
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CALL store_mem_sr
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CALL send_back
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CALL clear_regs
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CALL read_mem_lrs
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CALL send_back
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; Write with SRS, read with LR
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LRI $AR0, #0xC00C
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CALL create_pattern
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CALL store_mem_srs
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CALL send_back
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CALL clear_regs
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CALL read_mem_lr
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CALL send_back
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; Write with SR, read with LRS
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LRI $AR0, #0xD00D
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CALL create_pattern
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CALL store_mem_srs
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CALL send_back
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CALL clear_regs
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CALL read_mem_lrs
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CALL send_back
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; We're done, DO NOT DELETE THIS LINE
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JMP end_of_test
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create_pattern:
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LRI $IX0, #0x0110
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MRR $AX0.L, $AR0
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ADDARN $AR0, $IX0
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MRR $AX1.L, $AR0
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ADDARN $AR0, $IX0
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MRR $AX0.H, $AR0
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ADDARN $AR0, $IX0
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MRR $AX1.H, $AR0
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ADDARN $AR0, $IX0
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MRR $AC0.L, $AR0
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ADDARN $AR0, $IX0
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MRR $AC1.L, $AR0
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ADDARN $AR0, $IX0
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MRR $AC0.M, $AR0
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ADDARN $AR0, $IX0
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MRR $AC1.M, $AR0
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ADDARN $AR0, $IX0
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; AC0.H and AC1.H have odd results since they're 8-bit sign-extended, but that's fine.
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MRR $AC0.H, $AR0
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ADDARN $AR0, $IX0
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MRR $AC1.H, $AR0
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RET
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clear_regs:
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LRI $AX0.L, #0x0000
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LRI $AX1.L, #0x0000
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LRI $AX0.H, #0x0000
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LRI $AX1.H, #0x0000
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LRI $AC0.L, #0x0000
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LRI $AC1.L, #0x0000
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LRI $AC0.M, #0x0000
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LRI $AC1.M, #0x0000
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LRI $AC0.H, #0x0000
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LRI $AC1.H, #0x0000
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RET
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read_mem_lr:
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LR $AX0.L, @0x0000
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LR $AX1.L, @0x0001
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LR $AX0.H, @0x0002
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LR $AX1.H, @0x0003
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LR $AC0.L, @0x0004
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LR $AC1.L, @0x0005
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LR $AC0.M, @0x0006
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LR $AC1.M, @0x0007
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RET
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read_mem_lrs:
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LRS $AX0.L, @0x00
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LRS $AX1.L, @0x01
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LRS $AX0.H, @0x02
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LRS $AX1.H, @0x03
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LRS $AC0.L, @0x04
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LRS $AC1.L, @0x05
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LRS $AC0.M, @0x06
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LRS $AC1.M, @0x07
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RET
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store_mem_sr:
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SR @0x0000, $AX0.L
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SR @0x0001, $AX1.L
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SR @0x0002, $AX0.H
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SR @0x0003, $AX1.H
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SR @0x0004, $AC0.L
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SR @0x0005, $AC1.L
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SR @0x0006, $AC0.M
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SR @0x0007, $AC1.M
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RET
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store_mem_srs:
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; For future compatibility these have been changed to cw.
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; The way the instructions were originally encoded is commented,
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; but this does not match their behavior.
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cw 0x2800 ; SRS @0x00, $AX0.L - actually SRSH @0x00, $AC0.H
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cw 0x2901 ; SRS @0x01, $AX1.L - actually SRSH @0x01, $AC1.H
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cw 0x2A02 ; SRS @0x02, $AX0.H - actually unknown, no store performed
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cw 0x2B03 ; SRS @0x03, $AX1.H - actually unknown, no store performed
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cw 0x2C04 ; SRS @0x04, $AC0.L
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cw 0x2D05 ; SRS @0x05, $AC1.L
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cw 0x2E06 ; SRS @0x06, $AC0.M
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cw 0x2F07 ; SRS @0x07, $AC1.M
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RET
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