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JitArm64: Fix gpr.GetReg usages in conditional code.

This commit is contained in:
degasus 2017-03-20 09:25:49 +01:00
parent 26bb26fe54
commit f7a52c0c35
2 changed files with 5 additions and 3 deletions
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3
Source/Core/Core/PowerPC/JitArm64/JitArm64_Branch.cpp
View File

@ -231,6 +231,8 @@ void JitArm64::bclrx(UGeckoInstruction inst)
(inst.BO & BO_DONT_DECREMENT_FLAG) == 0 || (inst.BO & BO_DONT_CHECK_CONDITION) == 0;
ARM64Reg WA = gpr.GetReg();
ARM64Reg WB = inst.LK ? gpr.GetReg() : INVALID_REG;
FixupBranch pCTRDontBranch;
if ((inst.BO & BO_DONT_DECREMENT_FLAG) == 0) // Decrement and test CTR
{
@ -263,7 +265,6 @@ void JitArm64::bclrx(UGeckoInstruction inst)
if (inst.LK)
{
ARM64Reg WB = gpr.GetReg();
MOVI2R(WB, js.compilerPC + 4);
STR(INDEX_UNSIGNED, WB, PPC_REG, PPCSTATE_OFF(spr[SPR_LR]));
gpr.Unlock(WB);

5
Source/Core/Core/PowerPC/JitArm64/JitArm64_LoadStore.cpp
View File

@ -380,6 +380,9 @@ void JitArm64::lXX(UGeckoInstruction inst)
(SConfig::GetInstance().bWii && js.op[1].inst.hex == 0x2C000000)) && // cmpXwi r0,0
js.op[2].inst.hex == 0x4182fff8) // beq -8
{
ARM64Reg WA = gpr.GetReg();
ARM64Reg XA = EncodeRegTo64(WA);
// if it's still 0, we can wait until the next event
FixupBranch noIdle = CBNZ(gpr.R(d));
@ -390,8 +393,6 @@ void JitArm64::lXX(UGeckoInstruction inst)
gpr.Flush(FLUSH_MAINTAIN_STATE);
fpr.Flush(FLUSH_MAINTAIN_STATE);
ARM64Reg WA = gpr.GetReg();
ARM64Reg XA = EncodeRegTo64(WA);
MOVP2R(XA, &CoreTiming::Idle);
BLR(XA);
gpr.Unlock(WA);