From f5e7e70cc5078915656aafaa7c6ccb3a38d62b05 Mon Sep 17 00:00:00 2001 From: Bram Speeckaert Date: Tue, 1 Nov 2022 11:24:16 +0100 Subject: [PATCH] JitArm64: cmp - Refactor --- .../PowerPC/JitArm64/JitArm64_Integer.cpp | 25 +++++++++---------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp index 6c0d159be8..2b46e80e70 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp @@ -578,25 +578,24 @@ void JitArm64::cmp(UGeckoInstruction inst) s64 A = static_cast(gpr.GetImm(a)); s64 B = static_cast(gpr.GetImm(b)); MOVI2R(CR, A - B); - return; } - - if (gpr.IsImm(b) && !gpr.GetImm(b)) + else if (gpr.IsImm(b) && !gpr.GetImm(b)) { SXTW(CR, gpr.R(a)); - return; } + else + { + ARM64Reg WA = gpr.GetReg(); + ARM64Reg XA = EncodeRegTo64(WA); + ARM64Reg RA = gpr.R(a); + ARM64Reg RB = gpr.R(b); - ARM64Reg WA = gpr.GetReg(); - ARM64Reg XA = EncodeRegTo64(WA); - ARM64Reg RA = gpr.R(a); - ARM64Reg RB = gpr.R(b); + SXTW(XA, RA); + SXTW(CR, RB); + SUB(CR, XA, CR); - SXTW(XA, RA); - SXTW(CR, RB); - SUB(CR, XA, CR); - - gpr.Unlock(WA); + gpr.Unlock(WA); + } } void JitArm64::cmpl(UGeckoInstruction inst)