ShuriZma
/
dolphin
mirror of https://github.com/dolphin-emu/dolphin.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Jit64: use overloaded IsSimpleReg() where useful

This commit is contained in:
Tillmann Karras 2015-08-04 21:21:37 +02:00
parent a3476415f6
commit f5a10bddee
2 changed files with 11 additions and 11 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
Source/Core/Core/PowerPC/Jit64/JitRegCache.cpp
View File

@ -289,7 +289,7 @@ void RegCache::BindToRegister(size_t i, bool doLoad, bool makeDirty)
LoadRegister(i, xr); LoadRegister(i, xr);
for (size_t j = 0; j < regs.size(); j++) for (size_t j = 0; j < regs.size(); j++)
{ {
if (i != j && regs[j].location.IsSimpleReg() && regs[j].location.GetSimpleReg() == xr) if (i != j && regs[j].location.IsSimpleReg(xr))
{ {
Crash(); Crash();
} }

20
Source/Core/Core/PowerPC/JitCommon/Jit_Util.cpp
View File

@ -476,7 +476,7 @@ bool EmuCodeBlock::WriteToConstAddress(int accessSize, OpArg arg, u32 address, B
// fun tricks... // fun tricks...
if (jit->jo.optimizeGatherPipe && PowerPC::IsOptimizableGatherPipeWrite(address)) if (jit->jo.optimizeGatherPipe && PowerPC::IsOptimizableGatherPipeWrite(address))
{ {
if (!arg.IsSimpleReg() || arg.GetSimpleReg() != RSCRATCH) if (!arg.IsSimpleReg(RSCRATCH))
MOV(accessSize, R(RSCRATCH), arg); MOV(accessSize, R(RSCRATCH), arg);
UnsafeWriteGatherPipe(accessSize); UnsafeWriteGatherPipe(accessSize);
@ -654,7 +654,7 @@ void EmuCodeBlock::ForceSinglePrecision(X64Reg output, const OpArg& input, bool
MOVDDUP(output, R(output)); MOVDDUP(output, R(output));
} }
} }
else if (!input.IsSimpleReg() || input.GetSimpleReg() != output) else if (!input.IsSimpleReg(output))
{ {
if (duplicate) if (duplicate)
MOVDDUP(output, input); MOVDDUP(output, input);
@ -667,7 +667,7 @@ void EmuCodeBlock::ForceSinglePrecision(X64Reg output, const OpArg& input, bool
void EmuCodeBlock::avx_op(void (XEmitter::*avxOp)(X64Reg, X64Reg, const OpArg&), void (XEmitter::*sseOp)(X64Reg, const OpArg&), void EmuCodeBlock::avx_op(void (XEmitter::*avxOp)(X64Reg, X64Reg, const OpArg&), void (XEmitter::*sseOp)(X64Reg, const OpArg&),
X64Reg regOp, const OpArg& arg1, const OpArg& arg2, bool packed, bool reversible) X64Reg regOp, const OpArg& arg1, const OpArg& arg2, bool packed, bool reversible)
{ {
if (arg1.IsSimpleReg() && regOp == arg1.GetSimpleReg()) if (arg1.IsSimpleReg(regOp))
{ {
(this->*sseOp)(regOp, arg2); (this->*sseOp)(regOp, arg2);
} }
@ -675,7 +675,7 @@ void EmuCodeBlock::avx_op(void (XEmitter::*avxOp)(X64Reg, X64Reg, const OpArg&),
{ {
(this->*avxOp)(regOp, arg1.GetSimpleReg(), arg2); (this->*avxOp)(regOp, arg1.GetSimpleReg(), arg2);
} }
else if (arg2.IsSimpleReg() && arg2.GetSimpleReg() == regOp) else if (arg2.IsSimpleReg(regOp))
{ {
if (reversible) if (reversible)
{ {
@ -684,7 +684,7 @@ void EmuCodeBlock::avx_op(void (XEmitter::*avxOp)(X64Reg, X64Reg, const OpArg&),
else else
{ {
// The ugly case: regOp == arg2 without AVX, or with arg1 == memory // The ugly case: regOp == arg2 without AVX, or with arg1 == memory
if (!arg1.IsSimpleReg() || arg1.GetSimpleReg() != XMM0) if (!arg1.IsSimpleReg(XMM0))
MOVAPD(XMM0, arg1); MOVAPD(XMM0, arg1);
if (cpu_info.bAVX) if (cpu_info.bAVX)
{ {
@ -714,7 +714,7 @@ void EmuCodeBlock::avx_op(void (XEmitter::*avxOp)(X64Reg, X64Reg, const OpArg&),
void EmuCodeBlock::avx_op(void (XEmitter::*avxOp)(X64Reg, X64Reg, const OpArg&, u8), void (XEmitter::*sseOp)(X64Reg, const OpArg&, u8), void EmuCodeBlock::avx_op(void (XEmitter::*avxOp)(X64Reg, X64Reg, const OpArg&, u8), void (XEmitter::*sseOp)(X64Reg, const OpArg&, u8),
X64Reg regOp, const OpArg& arg1, const OpArg& arg2, u8 imm) X64Reg regOp, const OpArg& arg1, const OpArg& arg2, u8 imm)
{ {
if (arg1.IsSimpleReg() && regOp == arg1.GetSimpleReg()) if (arg1.IsSimpleReg(regOp))
{ {
(this->*sseOp)(regOp, arg2, imm); (this->*sseOp)(regOp, arg2, imm);
} }
@ -722,10 +722,10 @@ void EmuCodeBlock::avx_op(void (XEmitter::*avxOp)(X64Reg, X64Reg, const OpArg&,
{ {
(this->*avxOp)(regOp, arg1.GetSimpleReg(), arg2, imm); (this->*avxOp)(regOp, arg1.GetSimpleReg(), arg2, imm);
} }
else if (arg2.IsSimpleReg() && arg2.GetSimpleReg() == regOp) else if (arg2.IsSimpleReg(regOp))
{ {
// The ugly case: regOp == arg2 without AVX, or with arg1 == memory // The ugly case: regOp == arg2 without AVX, or with arg1 == memory
if (!arg1.IsSimpleReg() || arg1.GetSimpleReg() != XMM0) if (!arg1.IsSimpleReg(XMM0))
MOVAPD(XMM0, arg1); MOVAPD(XMM0, arg1);
if (cpu_info.bAVX) if (cpu_info.bAVX)
{ {
@ -764,14 +764,14 @@ void EmuCodeBlock::Force25BitPrecision(X64Reg output, const OpArg& input, X64Reg
} }
else else
{ {
if (!input.IsSimpleReg() || input.GetSimpleReg() != output) if (!input.IsSimpleReg(output))
MOVAPD(output, input); MOVAPD(output, input);
avx_op(&XEmitter::VPAND, &XEmitter::PAND, tmp, R(output), M(psRoundBit), true, true); avx_op(&XEmitter::VPAND, &XEmitter::PAND, tmp, R(output), M(psRoundBit), true, true);
PAND(output, M(psMantissaTruncate)); PAND(output, M(psMantissaTruncate));
PADDQ(output, R(tmp)); PADDQ(output, R(tmp));
} }
} }
else if (!input.IsSimpleReg() || input.GetSimpleReg() != output) else if (!input.IsSimpleReg(output))
{ {
MOVAPD(output, input); MOVAPD(output, input);
} }