From f4e1f48b4fcfde29a50d297b5f7ec62377222442 Mon Sep 17 00:00:00 2001 From: Lioncash Date: Tue, 29 Dec 2020 14:32:08 -0500 Subject: [PATCH] DSPCore: Make IRAM CRC and step counter private We can construct an API around these two members to allow them to be private. --- Source/Core/Core/DSP/DSPCore.cpp | 4 ++-- Source/Core/Core/DSP/DSPCore.h | 14 ++++++++++---- Source/Core/Core/DSP/DSPHWInterface.cpp | 2 +- .../Core/Core/DSP/Interpreter/DSPInterpreter.cpp | 2 +- Source/Core/Core/HW/DSPLLE/DSPHost.cpp | 2 +- 5 files changed, 15 insertions(+), 9 deletions(-) diff --git a/Source/Core/Core/DSP/DSPCore.cpp b/Source/Core/Core/DSP/DSPCore.cpp index a12bee76c2..ca5eff4269 100644 --- a/Source/Core/Core/DSP/DSPCore.cpp +++ b/Source/Core/Core/DSP/DSPCore.cpp @@ -119,7 +119,7 @@ SDSP::~SDSP() = default; bool SDSP::Initialize(const DSPInitOptions& opts) { - step_counter = 0; + m_step_counter = 0; m_accelerator = std::make_unique(*this); irom = static_cast(Common::AllocateMemoryPages(DSP_IROM_BYTE_SIZE)); @@ -384,7 +384,7 @@ void SDSP::DoState(PointerWrap& p) p.Do(stack); } - p.Do(step_counter); + p.Do(m_step_counter); p.DoArray(m_ifx_regs); m_accelerator->DoState(p); p.Do(m_mailbox[0]); diff --git a/Source/Core/Core/DSP/DSPCore.h b/Source/Core/Core/DSP/DSPCore.h index e2f43f391c..298019aceb 100644 --- a/Source/Core/Core/DSP/DSPCore.h +++ b/Source/Core/Core/DSP/DSPCore.h @@ -396,6 +396,12 @@ struct SDSP // Writes a value to a given register. void WriteRegister(size_t reg, u16 val); + // Advances the step counter used for debugging purposes. + void AdvanceStepCounter() { ++m_step_counter; } + + // Sets the calculated IRAM CRC for debugging purposes. + void SetIRAMCRC(u32 crc) { m_iram_crc = crc; } + // Saves and loads any necessary state. void DoState(PointerWrap& p); @@ -425,10 +431,6 @@ struct SDSP // the stack overflows, you're screwed. u16 reg_stacks[4][DSP_STACK_DEPTH]{}; - // For debugging. - u32 iram_crc = 0; - u64 step_counter = 0; - // When state saving, all of the above can just be memcpy'd into the save state. // The below needs special handling. u16* iram = nullptr; @@ -450,6 +452,10 @@ private: u16 ReadIFXImpl(u16 address); + // For debugging. + u32 m_iram_crc = 0; + u64 m_step_counter = 0; + // Accelerator / DMA / other hardware registers. Not GPRs. std::array m_ifx_regs{}; diff --git a/Source/Core/Core/DSP/DSPHWInterface.cpp b/Source/Core/Core/DSP/DSPHWInterface.cpp index f182d7460f..ec5d449057 100644 --- a/Source/Core/Core/DSP/DSPHWInterface.cpp +++ b/Source/Core/Core/DSP/DSPHWInterface.cpp @@ -290,7 +290,7 @@ const u8* SDSP::IDMAIn(u16 dsp_addr, u32 addr, u32 size) Host::CodeLoaded(m_dsp_core, addr, size); NOTICE_LOG_FMT(DSPLLE, "*** Copy new UCode from {:#010x} to {:#06x} (crc: {:#08x})", addr, - dsp_addr, iram_crc); + dsp_addr, m_iram_crc); return reinterpret_cast(iram) + dsp_addr; } diff --git a/Source/Core/Core/DSP/Interpreter/DSPInterpreter.cpp b/Source/Core/Core/DSP/Interpreter/DSPInterpreter.cpp index b900d0585c..c142123fdc 100644 --- a/Source/Core/Core/DSP/Interpreter/DSPInterpreter.cpp +++ b/Source/Core/Core/DSP/Interpreter/DSPInterpreter.cpp @@ -49,7 +49,7 @@ void Interpreter::Step() auto& state = m_dsp_core.DSPState(); m_dsp_core.CheckExceptions(); - state.step_counter++; + state.AdvanceStepCounter(); const u16 opc = state.FetchInstruction(); ExecuteInstruction(UDSPInstruction{opc}); diff --git a/Source/Core/Core/HW/DSPLLE/DSPHost.cpp b/Source/Core/Core/HW/DSPLLE/DSPHost.cpp index 65e26ce238..f02472a081 100644 --- a/Source/Core/Core/HW/DSPLLE/DSPHost.cpp +++ b/Source/Core/Core/HW/DSPLLE/DSPHost.cpp @@ -77,7 +77,7 @@ void CodeLoaded(DSPCore& dsp, const u8* ptr, size_t size) { auto& state = dsp.DSPState(); const u32 iram_crc = Common::HashEctor(ptr, size); - state.iram_crc = iram_crc; + state.SetIRAMCRC(iram_crc); if (SConfig::GetInstance().m_DumpUCode) {