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Merge pull request #2882 from lioncash/namespace 

Jit: Remove unnecessary namespace prefixes
This commit is contained in:
Lioncash 2015-08-20 05:38:29 -04:00
parent cb264df64c 95c57fcec1
commit f481a306c2
4 changed files with 7 additions and 7 deletions
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4
Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp
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@ -128,7 +128,7 @@ void Jit64::FinalizeCarryOverflow(bool oe, bool inv)
// to be recalculated and haven't been clobbered. Keep in mind not all instructions set // to be recalculated and haven't been clobbered. Keep in mind not all instructions set
// sufficient flags -- for example, the flags from SHL/SHR are *not* sufficient for LT/GT // sufficient flags -- for example, the flags from SHL/SHR are *not* sufficient for LT/GT
// branches, only EQ. // branches, only EQ.
void Jit64::ComputeRC(const Gen::OpArg & arg, bool needs_test, bool needs_sext) void Jit64::ComputeRC(const OpArg& arg, bool needs_test, bool needs_sext)
{ {
_assert_msg_(DYNA_REC, arg.IsSimpleReg() || arg.IsImm(), "Invalid ComputeRC operand"); _assert_msg_(DYNA_REC, arg.IsSimpleReg() || arg.IsImm(), "Invalid ComputeRC operand");
if (arg.IsImm()) if (arg.IsImm())
@ -215,7 +215,7 @@ static u32 Xor(u32 a, u32 b)
return a ^ b; return a ^ b;
} }
void Jit64::regimmop(int d, int a, bool binary, u32 value, Operation doop, void (XEmitter::*op)(int, const Gen::OpArg&, const Gen::OpArg&), bool Rc, bool carry) void Jit64::regimmop(int d, int a, bool binary, u32 value, Operation doop, void (XEmitter::*op)(int, const OpArg&, const OpArg&), bool Rc, bool carry)
{ {
bool needs_test = false; bool needs_test = false;
gpr.Lock(d, a); gpr.Lock(d, a);

2
Source/Core/Core/PowerPC/Jit64/Jit_LoadStore.cpp
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@ -162,7 +162,7 @@ void Jit64::lXXx(UGeckoInstruction inst)
s32 loadOffset = 0; s32 loadOffset = 0;
// Prepare address operand // Prepare address operand
Gen::OpArg opAddress; OpArg opAddress;
if (!update && !a) if (!update && !a)
{ {
if (inst.OPCD == 31) if (inst.OPCD == 31)

4
Source/Core/Core/PowerPC/Jit64/Jit_SystemRegisters.cpp
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@ -11,7 +11,7 @@
using namespace Gen; using namespace Gen;
void Jit64::GetCRFieldBit(int field, int bit, Gen::X64Reg out, bool negate) void Jit64::GetCRFieldBit(int field, int bit, X64Reg out, bool negate)
{ {
switch (bit) switch (bit)
{ {
@ -40,7 +40,7 @@ void Jit64::GetCRFieldBit(int field, int bit, Gen::X64Reg out, bool negate)
} }
} }
void Jit64::SetCRFieldBit(int field, int bit, Gen::X64Reg in) void Jit64::SetCRFieldBit(int field, int bit, X64Reg in)
{ {
MOV(64, R(RSCRATCH2), PPCSTATE(cr_val[field])); MOV(64, R(RSCRATCH2), PPCSTATE(cr_val[field]));
MOVZX(32, 8, in, R(in)); MOVZX(32, 8, in, R(in));

4
Source/Core/Core/PowerPC/Jit64IL/JitIL.cpp
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@ -375,7 +375,7 @@ void JitIL::WriteExit(u32 destination)
b->linkData.push_back(linkData); b->linkData.push_back(linkData);
} }
void JitIL::WriteExitDestInOpArg(const Gen::OpArg& arg) void JitIL::WriteExitDestInOpArg(const OpArg& arg)
{ {
MOV(32, PPCSTATE(pc), arg); MOV(32, PPCSTATE(pc), arg);
Cleanup(); Cleanup();
@ -387,7 +387,7 @@ void JitIL::WriteExitDestInOpArg(const Gen::OpArg& arg)
JMP(asm_routines.dispatcher, true); JMP(asm_routines.dispatcher, true);
} }
void JitIL::WriteRfiExitDestInOpArg(const Gen::OpArg& arg) void JitIL::WriteRfiExitDestInOpArg(const OpArg& arg)
{ {
MOV(32, PPCSTATE(pc), arg); MOV(32, PPCSTATE(pc), arg);
MOV(32, PPCSTATE(npc), arg); MOV(32, PPCSTATE(npc), arg);