LLE JIT: Implemented the addr, lsl and lsl16 instructions in the JIT (x64 only).
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6542 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
parent
8fd825c18c
commit
f353f80302
|
@ -20,6 +20,7 @@ set(SRCS Src/assemble.cpp
|
|||
Src/DSPTables.cpp
|
||||
Src/Jit/DSPJitExtOps.cpp
|
||||
Src/Jit/DSPJitCCUtil.cpp
|
||||
Src/Jit/DSPJitArithmetic.cpp
|
||||
Src/Jit/DSPJitMultiplier.cpp
|
||||
Src/Jit/DSPJitUtil.cpp
|
||||
Src/Jit/DSPJitMisc.cpp)
|
||||
|
|
|
@ -458,6 +458,10 @@
|
|||
RelativePath=".\Src\DSPEmitter.h"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath=".\Src\Jit\DSPJitArithmetic.cpp"
|
||||
>
|
||||
</File>
|
||||
<File
|
||||
RelativePath=".\Src\Jit\DSPJitCCUtil.cpp"
|
||||
>
|
||||
|
|
|
@ -116,6 +116,11 @@ public:
|
|||
void mrr(const UDSPInstruction opc);
|
||||
void nx(const UDSPInstruction opc);
|
||||
|
||||
// Arithmetic
|
||||
void addr(const UDSPInstruction opc);
|
||||
void lsl16(const UDSPInstruction opc);
|
||||
void lsl(const UDSPInstruction opc);
|
||||
|
||||
// Multipliers
|
||||
void get_multiply_prod();
|
||||
void multiply();
|
||||
|
|
|
@ -149,7 +149,7 @@ const DSPOPCTemplate opcodes[] =
|
|||
{"SBCLR", 0x1200, 0xff00, DSPInterpreter::sbclr, &DSPEmitter::sbclr, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, false, false, false},
|
||||
{"SBSET", 0x1300, 0xff00, DSPInterpreter::sbset, &DSPEmitter::sbset, 1, 1, {{P_IMM, 1, 0, 0, 0x0007}}, false, false, false},
|
||||
|
||||
{"LSL", 0x1400, 0xfec0, DSPInterpreter::lsl, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false},
|
||||
{"LSL", 0x1400, 0xfec0, DSPInterpreter::lsl, &DSPEmitter::lsl, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false},
|
||||
{"LSR", 0x1440, 0xfec0, DSPInterpreter::lsr, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false},
|
||||
{"ASL", 0x1480, 0xfec0, DSPInterpreter::asl, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false},
|
||||
{"ASR", 0x14c0, 0xfec0, DSPInterpreter::asr, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_IMM, 1, 0, 0, 0x003f}}, false, false, false},
|
||||
|
@ -220,7 +220,7 @@ const DSPOPCTemplate opcodes[] =
|
|||
{"ASRNR", 0x3e80, 0xfe80, DSPInterpreter::asrnr, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACCM_D, 1, 0, 8, 0x0100}}, true, false, false},
|
||||
|
||||
//4
|
||||
{"ADDR", 0x4000, 0xf800, DSPInterpreter::addr, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false, false},
|
||||
{"ADDR", 0x4000, 0xf800, DSPInterpreter::addr, &DSPEmitter::addr, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_REG18, 1, 0, 9, 0x0600}}, true, false, false},
|
||||
{"ADDAX", 0x4800, 0xfc00, DSPInterpreter::addax, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_AX, 1, 0, 9, 0x0200}}, true, false, false},
|
||||
{"ADD", 0x4c00, 0xfe00, DSPInterpreter::add, NULL, 1, 2, {{P_ACC, 1, 0, 8, 0x0100}, {P_ACC_D, 1, 0, 8, 0x0100}}, true, false, false},
|
||||
{"ADDP", 0x4e00, 0xfe00, DSPInterpreter::addp, NULL, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false},
|
||||
|
@ -290,7 +290,7 @@ const DSPOPCTemplate opcodes[] =
|
|||
{"MSUBC", 0xec00, 0xfc00, DSPInterpreter::msubc, &DSPEmitter::msubc, 1, 2, {{P_ACCM, 1, 0, 9, 0x0200}, {P_REG19, 1, 0, 7, 0x0100}}, true, false, false},
|
||||
|
||||
//f
|
||||
{"LSL16", 0xf000, 0xfe00, DSPInterpreter::lsl16, NULL, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false},
|
||||
{"LSL16", 0xf000, 0xfe00, DSPInterpreter::lsl16, &DSPEmitter::lsl16, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false},
|
||||
{"MADD", 0xf200, 0xfe00, DSPInterpreter::madd, &DSPEmitter::madd, 1, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true, false, false},
|
||||
{"LSR16", 0xf400, 0xfe00, DSPInterpreter::lsr16, NULL, 1, 1, {{P_ACC, 1, 0, 8, 0x0100}}, true, false, false},
|
||||
{"MSUB", 0xf600, 0xfe00, DSPInterpreter::msub, &DSPEmitter::msub, 1, 2, {{P_REG18, 1, 0, 8, 0x0100}, {P_REG1A, 1, 0, 8, 0x0100}}, true, false, false},
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -26,7 +26,8 @@
|
|||
#include "ABI.h"
|
||||
using namespace Gen;
|
||||
|
||||
// In: RAX: s64 _Value,
|
||||
// In: RAX: s64 _Value
|
||||
// In: RCX: 1 = carry, 2 = overflow
|
||||
// Clobbers RDX
|
||||
void DSPEmitter::Update_SR_Register64(bool carry, bool overflow)
|
||||
{
|
||||
|
@ -36,18 +37,18 @@ void DSPEmitter::Update_SR_Register64(bool carry, bool overflow)
|
|||
|
||||
// 0x01
|
||||
// g_dsp.r[DSP_REG_SR] |= SR_CARRY;
|
||||
if (carry)
|
||||
{
|
||||
OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_CARRY));
|
||||
}
|
||||
TEST(8, R(RSI), Imm8(1));
|
||||
FixupBranch noCarry = J_CC(CC_NZ);
|
||||
OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_CARRY));
|
||||
SetJumpTarget(noCarry);
|
||||
|
||||
// 0x02 and 0x80
|
||||
// g_dsp.r[DSP_REG_SR] |= SR_OVERFLOW;
|
||||
// g_dsp.r[DSP_REG_SR] |= SR_OVERFLOW_STICKY;
|
||||
if (overflow)
|
||||
{
|
||||
OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_OVERFLOW | SR_OVERFLOW_STICKY));
|
||||
}
|
||||
TEST(8, R(RSI), Imm8(2));
|
||||
FixupBranch noOverflow = J_CC(CC_NZ);
|
||||
OR(16, MDisp(R11, DSP_REG_SR * 2), Imm16(SR_OVERFLOW | SR_OVERFLOW_STICKY));
|
||||
SetJumpTarget(noOverflow);
|
||||
|
||||
// // 0x04
|
||||
// if (_Value == 0) g_dsp.r[DSP_REG_SR] |= SR_ARITH_ZERO;
|
||||
|
|
|
@ -26,6 +26,7 @@ files = [
|
|||
"Jit/DSPJitExtOps.cpp",
|
||||
"Jit/DSPJitUtil.cpp",
|
||||
"Jit/DSPJitCCUtil.cpp",
|
||||
"Jit/DSPJitArithmetic.cpp",
|
||||
"Jit/DSPJitMultiplier.cpp",
|
||||
"Jit/DSPJitMisc.cpp",
|
||||
]
|
||||
|
|
Loading…
Reference in New Issue