PowerPC: Implement PI interrupt for uncached unaligned writes

This commit is contained in:
JosJuice 2021-07-26 17:48:47 +02:00
parent 543ed8a97c
commit f333c0949f
1 changed files with 6 additions and 0 deletions

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@ -18,6 +18,7 @@
#include "Core/HW/GPFifo.h"
#include "Core/HW/MMIO.h"
#include "Core/HW/Memmap.h"
#include "Core/HW/ProcessorInterface.h"
#include "Core/PowerPC/JitInterface.h"
#include "Core/PowerPC/PowerPC.h"
@ -368,6 +369,11 @@ static void WriteToHardware(u32 em_address, const u32 data, const u32 size)
// behavior for write-through/cache-inhibited writes with a start address or end address that
// isn't 32-bit aligned. See https://bugs.dolphin-emu.org/issues/12565 for details.
// TODO: This interrupt is supposed to have associated cause and address registers
// TODO: This should trigger the hwtest's interrupt handling, but it does not seem to
// (https://github.com/dolphin-emu/hwtests/pull/42)
ProcessorInterface::SetInterrupt(ProcessorInterface::INT_CAUSE_PI);
const u32 rotated_data = Common::RotateRight(data, ((em_address & 0x3) + size) * 8);
for (u32 addr = em_address & ~0x7; addr < em_address + size; addr += 8)