MMIO: Port the VI MMIOs to the new interface.
This commit is contained in:
Pierre Bourdon
parent
a3f95c1e10
commit
f1dba04be7
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@ -310,11 +310,13 @@ void InitHWMemFuncsWii()
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void InitMMIO(MMIO::Mapping* mmio)
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{
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VideoInterface::RegisterMMIO(mmio, 0xCC002000);
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ProcessorInterface::RegisterMMIO(mmio, 0xCC003000);
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}
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void InitMMIOWii(MMIO::Mapping* mmio)
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{
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VideoInterface::RegisterMMIO(mmio, 0xCC002000);
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ProcessorInterface::RegisterMMIO(mmio, 0xCC003000);
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}
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@ -13,6 +13,7 @@
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#include "../CoreTiming.h"
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#include "SystemTimers.h"
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#include "StringUtil.h"
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#include "MMIO.h"
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#include "VideoBackendBase.h"
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#include "State.h"
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@ -182,268 +183,171 @@ void Init()
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UpdateParameters();
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}
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void SetRegionReg(char region)
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void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
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{
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if (!Core::g_CoreStartupParameter.bForceNTSCJ)
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m_DTVStatus.ntsc_j = region == 'J';
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}
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struct {
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u32 addr;
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u16* ptr;
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} directly_mapped_vars[] = {
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{ VI_VERTICAL_TIMING, &m_VerticalTimingRegister.Hex },
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{ VI_HORIZONTAL_TIMING_0_HI, &m_HTiming0.Hi },
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{ VI_HORIZONTAL_TIMING_0_LO, &m_HTiming0.Lo },
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{ VI_HORIZONTAL_TIMING_1_HI, &m_HTiming1.Hi },
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{ VI_HORIZONTAL_TIMING_1_LO, &m_HTiming1.Lo },
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{ VI_VBLANK_TIMING_ODD_HI, &m_VBlankTimingOdd.Hi },
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{ VI_VBLANK_TIMING_ODD_LO, &m_VBlankTimingOdd.Lo },
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{ VI_VBLANK_TIMING_EVEN_HI, &m_VBlankTimingEven.Hi },
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{ VI_VBLANK_TIMING_EVEN_LO, &m_VBlankTimingEven.Lo },
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{ VI_BURST_BLANKING_ODD_HI, &m_BurstBlankingOdd.Hi },
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{ VI_BURST_BLANKING_ODD_LO, &m_BurstBlankingOdd.Lo },
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{ VI_BURST_BLANKING_EVEN_HI, &m_BurstBlankingEven.Hi },
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{ VI_BURST_BLANKING_EVEN_LO, &m_BurstBlankingEven.Lo },
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{ VI_FB_LEFT_TOP_LO, &m_XFBInfoTop.Lo },
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{ VI_FB_RIGHT_TOP_LO, &m_3DFBInfoTop.Lo },
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{ VI_FB_LEFT_BOTTOM_LO, &m_XFBInfoBottom.Lo },
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{ VI_FB_RIGHT_BOTTOM_LO, &m_3DFBInfoBottom.Lo },
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{ VI_PRERETRACE_LO, &m_InterruptRegister[0].Lo },
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{ VI_POSTRETRACE_LO, &m_InterruptRegister[1].Lo },
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{ VI_DISPLAY_INTERRUPT_2_LO, &m_InterruptRegister[2].Lo },
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{ VI_DISPLAY_INTERRUPT_3_LO, &m_InterruptRegister[3].Lo },
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{ VI_DISPLAY_LATCH_0_HI, &m_LatchRegister[0].Hi },
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{ VI_DISPLAY_LATCH_0_LO, &m_LatchRegister[0].Lo },
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{ VI_DISPLAY_LATCH_1_HI, &m_LatchRegister[1].Hi },
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{ VI_DISPLAY_LATCH_1_LO, &m_LatchRegister[1].Lo },
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{ VI_HSCALEW, &m_HorizontalStepping.Hex },
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{ VI_HSCALER, &m_HorizontalScaling.Hex },
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{ VI_FILTER_COEF_0_HI, &m_FilterCoefTables.Tables02[0].Hi },
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{ VI_FILTER_COEF_0_LO, &m_FilterCoefTables.Tables02[0].Lo },
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{ VI_FILTER_COEF_1_HI, &m_FilterCoefTables.Tables02[1].Hi },
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{ VI_FILTER_COEF_1_LO, &m_FilterCoefTables.Tables02[1].Lo },
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{ VI_FILTER_COEF_2_HI, &m_FilterCoefTables.Tables02[2].Hi },
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{ VI_FILTER_COEF_2_LO, &m_FilterCoefTables.Tables02[2].Lo },
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{ VI_FILTER_COEF_3_HI, &m_FilterCoefTables.Tables36[0].Hi },
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{ VI_FILTER_COEF_3_LO, &m_FilterCoefTables.Tables36[0].Lo },
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{ VI_FILTER_COEF_4_HI, &m_FilterCoefTables.Tables36[1].Hi },
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{ VI_FILTER_COEF_4_LO, &m_FilterCoefTables.Tables36[1].Lo },
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{ VI_FILTER_COEF_5_HI, &m_FilterCoefTables.Tables36[2].Hi },
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{ VI_FILTER_COEF_5_LO, &m_FilterCoefTables.Tables36[2].Lo },
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{ VI_FILTER_COEF_6_HI, &m_FilterCoefTables.Tables36[3].Hi },
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{ VI_FILTER_COEF_6_LO, &m_FilterCoefTables.Tables36[3].Lo },
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{ VI_CLOCK, &m_Clock },
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{ VI_DTV_STATUS, &m_DTVStatus.Hex },
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{ VI_FBWIDTH, &m_FBWidth },
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{ VI_BORDER_BLANK_END, &m_BorderHBlank.Lo },
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{ VI_BORDER_BLANK_START, &m_BorderHBlank.Hi },
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};
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void Read8(u8& _uReturnValue, const u32 _iAddress)
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{
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// Just like 32bit VI transfers, this is technically not allowed,
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// but the hardware accepts it. Action Replay uses this.
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u16 val = 0;
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if ((_iAddress & 1) == 0)
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// Declare all the boilerplate direct MMIOs.
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for (auto& mapped_var : directly_mapped_vars)
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{
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Read16(val, _iAddress);
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_uReturnValue = (u8)(val >> 8);
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}
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else
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{
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Read16(val, _iAddress - 1);
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_uReturnValue = (u8)val;
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mmio->Register(base | mapped_var.addr,
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MMIO::DirectRead<u16>(mapped_var.ptr),
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MMIO::DirectWrite<u16>(mapped_var.ptr)
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);
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}
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INFO_LOG(VIDEOINTERFACE, "(r 8): 0x%02x, 0x%08x", _uReturnValue, _iAddress);
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}
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// XFB related MMIOs that require special handling on writes.
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mmio->Register(base | VI_FB_LEFT_TOP_HI,
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MMIO::DirectRead<u16>(&m_XFBInfoTop.Hi),
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MMIO::ComplexWrite<u16>([](u32, u16 val) {
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m_XFBInfoTop.Hi = val;
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if (m_XFBInfoTop.CLRPOFF) m_XFBInfoTop.POFF = 0;
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})
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);
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mmio->Register(base | VI_FB_LEFT_BOTTOM_HI,
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MMIO::DirectRead<u16>(&m_XFBInfoBottom.Hi),
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MMIO::ComplexWrite<u16>([](u32, u16 val) {
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m_XFBInfoBottom.Hi = val;
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if (m_XFBInfoBottom.CLRPOFF) m_XFBInfoBottom.POFF = 0;
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})
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);
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mmio->Register(base | VI_FB_RIGHT_TOP_HI,
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MMIO::DirectRead<u16>(&m_3DFBInfoTop.Hi),
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MMIO::ComplexWrite<u16>([](u32, u16 val) {
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m_3DFBInfoTop.Hi = val;
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if (m_3DFBInfoTop.CLRPOFF) m_3DFBInfoTop.POFF = 0;
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})
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);
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mmio->Register(base | VI_FB_RIGHT_BOTTOM_HI,
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MMIO::DirectRead<u16>(&m_3DFBInfoBottom.Hi),
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MMIO::ComplexWrite<u16>([](u32, u16 val) {
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m_3DFBInfoBottom.Hi = val;
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if (m_3DFBInfoBottom.CLRPOFF) m_3DFBInfoBottom.POFF = 0;
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})
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);
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void Read16(u16& _uReturnValue, const u32 _iAddress)
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{
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switch (_iAddress & 0xFFF)
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{
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case VI_VERTICAL_TIMING:
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_uReturnValue = m_VerticalTimingRegister.Hex;
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return;
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// MMIOs with unimplemented writes that trigger warnings.
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mmio->Register(base | VI_VERTICAL_BEAM_POSITION,
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MMIO::DirectRead<u16>(&m_VBeamPos),
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MMIO::ComplexWrite<u16>([](u32, u16 val) {
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WARN_LOG(VIDEOINTERFACE, "Changing vertical beam position to 0x%04x - not documented or implemented yet", val);
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})
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);
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mmio->Register(base | VI_HORIZONTAL_BEAM_POSITION,
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MMIO::DirectRead<u16>(&m_HBeamPos),
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MMIO::ComplexWrite<u16>([](u32, u16 val) {
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WARN_LOG(VIDEOINTERFACE, "Changing horizontal beam position to 0x%04x - not documented or implemented yet", val);
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})
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);
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case VI_CONTROL_REGISTER:
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_uReturnValue = m_DisplayControlRegister.Hex;
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return;
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// The following MMIOs are interrupts related and update interrupt status
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// on writes.
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mmio->Register(base | VI_PRERETRACE_HI,
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MMIO::DirectRead<u16>(&m_InterruptRegister[0].Hi),
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MMIO::ComplexWrite<u16>([](u32, u16 val) {
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m_InterruptRegister[0].Hi = val;
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UpdateInterrupts();
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})
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);
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mmio->Register(base | VI_POSTRETRACE_HI,
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MMIO::DirectRead<u16>(&m_InterruptRegister[1].Hi),
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MMIO::ComplexWrite<u16>([](u32, u16 val) {
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m_InterruptRegister[1].Hi = val;
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UpdateInterrupts();
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})
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);
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mmio->Register(base | VI_DISPLAY_INTERRUPT_2_HI,
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MMIO::DirectRead<u16>(&m_InterruptRegister[2].Hi),
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MMIO::ComplexWrite<u16>([](u32, u16 val) {
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m_InterruptRegister[2].Hi = val;
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UpdateInterrupts();
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})
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);
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mmio->Register(base | VI_DISPLAY_INTERRUPT_3_HI,
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MMIO::DirectRead<u16>(&m_InterruptRegister[3].Hi),
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MMIO::ComplexWrite<u16>([](u32, u16 val) {
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m_InterruptRegister[3].Hi = val;
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UpdateInterrupts();
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})
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);
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case VI_HORIZONTAL_TIMING_0_HI:
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_uReturnValue = m_HTiming0.Hi;
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break;
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case VI_HORIZONTAL_TIMING_0_LO:
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_uReturnValue = m_HTiming0.Lo;
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break;
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// Unknown anti-aliasing related MMIO register: puts a warning on log and
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// needs to shift/mask when reading/writing.
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mmio->Register(base | VI_UNK_AA_REG_HI,
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MMIO::ComplexRead<u16>([](u32) {
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return m_UnkAARegister >> 16;
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}),
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MMIO::ComplexWrite<u16>([](u32, u16 val) {
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m_UnkAARegister = (m_UnkAARegister & 0x0000FFFF) | ((u32)val << 16);
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WARN_LOG(VIDEOINTERFACE, "Writing to the unknown AA register (hi)");
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})
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);
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mmio->Register(base | VI_UNK_AA_REG_LO,
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MMIO::ComplexRead<u16>([](u32) {
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return m_UnkAARegister & 0xFFFF;
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}),
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MMIO::ComplexWrite<u16>([](u32, u16 val) {
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m_UnkAARegister = (m_UnkAARegister & 0xFFFF0000) | val;
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WARN_LOG(VIDEOINTERFACE, "Writing to the unknown AA register (lo)");
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})
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);
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case VI_HORIZONTAL_TIMING_1_HI:
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_uReturnValue = m_HTiming1.Hi;
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break;
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case VI_HORIZONTAL_TIMING_1_LO:
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_uReturnValue = m_HTiming1.Lo;
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break;
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case VI_VBLANK_TIMING_ODD_HI:
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_uReturnValue = m_VBlankTimingOdd.Hi;
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break;
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case VI_VBLANK_TIMING_ODD_LO:
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_uReturnValue = m_VBlankTimingOdd.Lo;
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break;
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case VI_VBLANK_TIMING_EVEN_HI:
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_uReturnValue = m_VBlankTimingEven.Hi;
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break;
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case VI_VBLANK_TIMING_EVEN_LO:
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_uReturnValue = m_VBlankTimingEven.Lo;
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break;
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case VI_BURST_BLANKING_ODD_HI:
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_uReturnValue = m_BurstBlankingOdd.Hi;
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break;
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case VI_BURST_BLANKING_ODD_LO:
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_uReturnValue = m_BurstBlankingOdd.Lo;
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break;
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case VI_BURST_BLANKING_EVEN_HI:
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_uReturnValue = m_BurstBlankingEven.Hi;
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break;
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case VI_BURST_BLANKING_EVEN_LO:
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_uReturnValue = m_BurstBlankingEven.Lo;
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break;
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case VI_FB_LEFT_TOP_HI:
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_uReturnValue = m_XFBInfoTop.Hi;
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break;
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case VI_FB_LEFT_TOP_LO:
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_uReturnValue = m_XFBInfoTop.Lo;
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break;
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case VI_FB_RIGHT_TOP_HI:
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_uReturnValue = m_3DFBInfoTop.Hi;
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break;
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case VI_FB_RIGHT_TOP_LO:
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_uReturnValue = m_3DFBInfoTop.Lo;
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break;
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case VI_FB_LEFT_BOTTOM_HI:
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_uReturnValue = m_XFBInfoBottom.Hi;
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break;
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case VI_FB_LEFT_BOTTOM_LO:
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_uReturnValue = m_XFBInfoBottom.Lo;
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break;
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case VI_FB_RIGHT_BOTTOM_HI:
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_uReturnValue = m_3DFBInfoBottom.Hi;
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break;
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case VI_FB_RIGHT_BOTTOM_LO:
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_uReturnValue = m_3DFBInfoBottom.Lo;
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break;
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case VI_VERTICAL_BEAM_POSITION:
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_uReturnValue = m_VBeamPos;
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return;
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case VI_HORIZONTAL_BEAM_POSITION:
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_uReturnValue = m_HBeamPos;
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return;
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// RETRACE STUFF ...
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case VI_PRERETRACE_HI:
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_uReturnValue = m_InterruptRegister[0].Hi;
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return;
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case VI_PRERETRACE_LO:
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_uReturnValue = m_InterruptRegister[0].Lo;
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return;
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case VI_POSTRETRACE_HI:
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_uReturnValue = m_InterruptRegister[1].Hi;
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return;
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case VI_POSTRETRACE_LO:
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_uReturnValue = m_InterruptRegister[1].Lo;
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return;
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case VI_DISPLAY_INTERRUPT_2_HI:
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_uReturnValue = m_InterruptRegister[2].Hi;
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return;
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case VI_DISPLAY_INTERRUPT_2_LO:
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_uReturnValue = m_InterruptRegister[2].Lo;
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return;
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case VI_DISPLAY_INTERRUPT_3_HI:
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_uReturnValue = m_InterruptRegister[3].Hi;
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return;
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case VI_DISPLAY_INTERRUPT_3_LO:
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_uReturnValue = m_InterruptRegister[3].Lo;
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return;
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case VI_DISPLAY_LATCH_0_HI:
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_uReturnValue = m_LatchRegister[0].Hi;
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break;
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case VI_DISPLAY_LATCH_0_LO:
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_uReturnValue = m_LatchRegister[0].Lo;
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break;
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case VI_DISPLAY_LATCH_1_HI:
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_uReturnValue = m_LatchRegister[1].Hi;
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break;
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case VI_DISPLAY_LATCH_1_LO:
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_uReturnValue = m_LatchRegister[1].Lo;
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break;
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case VI_HSCALEW:
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_uReturnValue = m_HorizontalStepping.Hex;
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break;
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case VI_HSCALER:
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_uReturnValue = m_HorizontalScaling.Hex;
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break;
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case VI_FILTER_COEF_0_HI:
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_uReturnValue = m_FilterCoefTables.Tables02[0].Hi;
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break;
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case VI_FILTER_COEF_0_LO:
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_uReturnValue = m_FilterCoefTables.Tables02[0].Lo;
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break;
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case VI_FILTER_COEF_1_HI:
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_uReturnValue = m_FilterCoefTables.Tables02[1].Hi;
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break;
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case VI_FILTER_COEF_1_LO:
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_uReturnValue = m_FilterCoefTables.Tables02[1].Lo;
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break;
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case VI_FILTER_COEF_2_HI:
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_uReturnValue = m_FilterCoefTables.Tables02[2].Hi;
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break;
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case VI_FILTER_COEF_2_LO:
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_uReturnValue = m_FilterCoefTables.Tables02[2].Lo;
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break;
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case VI_FILTER_COEF_3_HI:
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_uReturnValue = m_FilterCoefTables.Tables36[0].Hi;
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break;
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case VI_FILTER_COEF_3_LO:
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_uReturnValue = m_FilterCoefTables.Tables36[0].Lo;
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break;
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case VI_FILTER_COEF_4_HI:
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_uReturnValue = m_FilterCoefTables.Tables36[1].Hi;
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break;
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case VI_FILTER_COEF_4_LO:
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_uReturnValue = m_FilterCoefTables.Tables36[1].Lo;
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break;
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case VI_FILTER_COEF_5_HI:
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_uReturnValue = m_FilterCoefTables.Tables36[2].Hi;
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break;
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case VI_FILTER_COEF_5_LO:
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_uReturnValue = m_FilterCoefTables.Tables36[2].Lo;
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break;
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case VI_FILTER_COEF_6_HI:
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_uReturnValue = m_FilterCoefTables.Tables36[3].Hi;
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break;
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case VI_FILTER_COEF_6_LO:
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_uReturnValue = m_FilterCoefTables.Tables36[3].Lo;
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break;
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case VI_UNK_AA_REG_HI:
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_uReturnValue = (m_UnkAARegister & 0xffff0000) >> 16;
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WARN_LOG(VIDEOINTERFACE, "(r16) unknown AA register, not sure what it does :)");
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break;
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case VI_UNK_AA_REG_LO:
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_uReturnValue = m_UnkAARegister & 0x0000ffff;
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WARN_LOG(VIDEOINTERFACE, "(r16) unknown AA register, not sure what it does :)");
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break;
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case VI_CLOCK:
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_uReturnValue = m_Clock;
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break;
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case VI_DTV_STATUS:
|
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_uReturnValue = m_DTVStatus.Hex;
|
||||
break;
|
||||
|
||||
case VI_FBWIDTH:
|
||||
_uReturnValue = m_FBWidth;
|
||||
break;
|
||||
|
||||
case VI_BORDER_BLANK_END:
|
||||
_uReturnValue = m_BorderHBlank.Lo;
|
||||
break;
|
||||
case VI_BORDER_BLANK_START:
|
||||
_uReturnValue = m_BorderHBlank.Hi;
|
||||
break;
|
||||
|
||||
default:
|
||||
ERROR_LOG(VIDEOINTERFACE, "(r16) unknown reg %x", _iAddress & 0xfff);
|
||||
_uReturnValue = 0x0;
|
||||
break;
|
||||
}
|
||||
|
||||
DEBUG_LOG(VIDEOINTERFACE, "(r16): 0x%04x, 0x%08x", _uReturnValue, _iAddress);
|
||||
}
|
||||
|
||||
void Write16(const u16 _iValue, const u32 _iAddress)
|
||||
{
|
||||
DEBUG_LOG(VIDEOINTERFACE, "(w16): 0x%04x, 0x%08x",_iValue,_iAddress);
|
||||
|
||||
//Somewhere it sets screen width.. we need to communicate this to the gfx backend...
|
||||
|
||||
switch (_iAddress & 0xFFF)
|
||||
{
|
||||
case VI_VERTICAL_TIMING:
|
||||
m_VerticalTimingRegister.Hex = _iValue;
|
||||
break;
|
||||
|
||||
case VI_CONTROL_REGISTER:
|
||||
{
|
||||
UVIDisplayControlRegister tmpConfig(_iValue);
|
||||
// Control register writes only updates some select bits, and additional
|
||||
// processing needs to be done if a reset is requested.
|
||||
mmio->Register(base | VI_CONTROL_REGISTER,
|
||||
MMIO::DirectRead<u16>(&m_DisplayControlRegister.Hex),
|
||||
MMIO::ComplexWrite<u16>([](u32, u16 val) {
|
||||
UVIDisplayControlRegister tmpConfig(val);
|
||||
m_DisplayControlRegister.ENB = tmpConfig.ENB;
|
||||
m_DisplayControlRegister.NIN = tmpConfig.NIN;
|
||||
m_DisplayControlRegister.DLR = tmpConfig.DLR;
|
||||
|
|
@ -461,242 +365,66 @@ void Write16(const u16 _iValue, const u32 _iAddress)
|
|||
}
|
||||
|
||||
UpdateParameters();
|
||||
})
|
||||
);
|
||||
|
||||
// Map 8 bit reads (not writes) to 16 bit reads.
|
||||
for (int i = 0; i < 0x1000; i += 2)
|
||||
{
|
||||
mmio->Register(base | i,
|
||||
MMIO::ReadToLarger<u8>(mmio, base | i, 8),
|
||||
MMIO::InvalidWrite<u8>()
|
||||
);
|
||||
mmio->Register(base | (i + 1),
|
||||
MMIO::ReadToLarger<u8>(mmio, base | i, 0),
|
||||
MMIO::InvalidWrite<u8>()
|
||||
);
|
||||
}
|
||||
break;
|
||||
|
||||
case VI_HORIZONTAL_TIMING_0_HI:
|
||||
m_HTiming0.Hi = _iValue;
|
||||
break;
|
||||
case VI_HORIZONTAL_TIMING_0_LO:
|
||||
m_HTiming0.Lo = _iValue;
|
||||
break;
|
||||
|
||||
case VI_HORIZONTAL_TIMING_1_HI:
|
||||
m_HTiming1.Hi = _iValue;
|
||||
break;
|
||||
case VI_HORIZONTAL_TIMING_1_LO:
|
||||
m_HTiming1.Lo = _iValue;
|
||||
break;
|
||||
|
||||
case VI_VBLANK_TIMING_ODD_HI:
|
||||
m_VBlankTimingOdd.Hi = _iValue;
|
||||
break;
|
||||
case VI_VBLANK_TIMING_ODD_LO:
|
||||
m_VBlankTimingOdd.Lo = _iValue;
|
||||
break;
|
||||
|
||||
case VI_VBLANK_TIMING_EVEN_HI:
|
||||
m_VBlankTimingEven.Hi = _iValue;
|
||||
break;
|
||||
case VI_VBLANK_TIMING_EVEN_LO:
|
||||
m_VBlankTimingEven.Lo = _iValue;
|
||||
break;
|
||||
|
||||
case VI_BURST_BLANKING_ODD_HI:
|
||||
m_BurstBlankingOdd.Hi = _iValue;
|
||||
break;
|
||||
case VI_BURST_BLANKING_ODD_LO:
|
||||
m_BurstBlankingOdd.Lo = _iValue;
|
||||
break;
|
||||
|
||||
case VI_BURST_BLANKING_EVEN_HI:
|
||||
m_BurstBlankingEven.Hi = _iValue;
|
||||
break;
|
||||
case VI_BURST_BLANKING_EVEN_LO:
|
||||
m_BurstBlankingEven.Lo = _iValue;
|
||||
break;
|
||||
|
||||
case VI_FB_LEFT_TOP_HI:
|
||||
m_XFBInfoTop.Hi = _iValue;
|
||||
if (m_XFBInfoTop.CLRPOFF) m_XFBInfoTop.POFF = 0;
|
||||
break;
|
||||
case VI_FB_LEFT_TOP_LO:
|
||||
m_XFBInfoTop.Lo = _iValue;
|
||||
break;
|
||||
|
||||
case VI_FB_RIGHT_TOP_HI:
|
||||
m_3DFBInfoTop.Hi = _iValue;
|
||||
if (m_3DFBInfoTop.CLRPOFF) m_3DFBInfoTop.POFF = 0;
|
||||
break;
|
||||
case VI_FB_RIGHT_TOP_LO:
|
||||
m_3DFBInfoTop.Lo = _iValue;
|
||||
break;
|
||||
|
||||
case VI_FB_LEFT_BOTTOM_HI:
|
||||
m_XFBInfoBottom.Hi = _iValue;
|
||||
if (m_XFBInfoBottom.CLRPOFF) m_XFBInfoBottom.POFF = 0;
|
||||
break;
|
||||
case VI_FB_LEFT_BOTTOM_LO:
|
||||
m_XFBInfoBottom.Lo = _iValue;
|
||||
break;
|
||||
|
||||
case VI_FB_RIGHT_BOTTOM_HI:
|
||||
m_3DFBInfoBottom.Hi = _iValue;
|
||||
if (m_3DFBInfoBottom.CLRPOFF) m_3DFBInfoBottom.POFF = 0;
|
||||
break;
|
||||
case VI_FB_RIGHT_BOTTOM_LO:
|
||||
m_3DFBInfoBottom.Lo = _iValue;
|
||||
break;
|
||||
|
||||
case VI_VERTICAL_BEAM_POSITION:
|
||||
WARN_LOG(VIDEOINTERFACE, "Change Vertical Beam Position to 0x%04x - Not documented or implemented", _iValue);
|
||||
break;
|
||||
|
||||
case VI_HORIZONTAL_BEAM_POSITION:
|
||||
WARN_LOG(VIDEOINTERFACE, "Change Horizontal Beam Position to 0x%04x - Not documented or implemented", _iValue);
|
||||
break;
|
||||
|
||||
// RETRACE STUFF ...
|
||||
case VI_PRERETRACE_HI:
|
||||
m_InterruptRegister[0].Hi = _iValue;
|
||||
UpdateInterrupts();
|
||||
break;
|
||||
case VI_PRERETRACE_LO:
|
||||
m_InterruptRegister[0].Lo = _iValue;
|
||||
break;
|
||||
|
||||
case VI_POSTRETRACE_HI:
|
||||
m_InterruptRegister[1].Hi = _iValue;
|
||||
UpdateInterrupts();
|
||||
break;
|
||||
case VI_POSTRETRACE_LO:
|
||||
m_InterruptRegister[1].Lo = _iValue;
|
||||
break;
|
||||
|
||||
case VI_DISPLAY_INTERRUPT_2_HI:
|
||||
m_InterruptRegister[2].Hi = _iValue;
|
||||
UpdateInterrupts();
|
||||
break;
|
||||
case VI_DISPLAY_INTERRUPT_2_LO:
|
||||
m_InterruptRegister[2].Lo = _iValue;
|
||||
break;
|
||||
|
||||
case VI_DISPLAY_INTERRUPT_3_HI:
|
||||
m_InterruptRegister[3].Hi = _iValue;
|
||||
UpdateInterrupts();
|
||||
break;
|
||||
case VI_DISPLAY_INTERRUPT_3_LO:
|
||||
m_InterruptRegister[3].Lo = _iValue;
|
||||
break;
|
||||
|
||||
case VI_DISPLAY_LATCH_0_HI:
|
||||
m_LatchRegister[0].Hi = _iValue;
|
||||
break;
|
||||
case VI_DISPLAY_LATCH_0_LO:
|
||||
m_LatchRegister[0].Lo = _iValue;
|
||||
break;
|
||||
|
||||
case VI_DISPLAY_LATCH_1_HI:
|
||||
m_LatchRegister[1].Hi = _iValue;
|
||||
break;
|
||||
case VI_DISPLAY_LATCH_1_LO:
|
||||
m_LatchRegister[1].Lo = _iValue;
|
||||
break;
|
||||
|
||||
case VI_HSCALEW:
|
||||
m_HorizontalStepping.Hex = _iValue;
|
||||
break;
|
||||
|
||||
case VI_HSCALER:
|
||||
m_HorizontalScaling.Hex = _iValue;
|
||||
break;
|
||||
|
||||
case VI_FILTER_COEF_0_HI:
|
||||
m_FilterCoefTables.Tables02[0].Hi = _iValue;
|
||||
break;
|
||||
case VI_FILTER_COEF_0_LO:
|
||||
m_FilterCoefTables.Tables02[0].Lo = _iValue;
|
||||
break;
|
||||
case VI_FILTER_COEF_1_HI:
|
||||
m_FilterCoefTables.Tables02[1].Hi = _iValue;
|
||||
break;
|
||||
case VI_FILTER_COEF_1_LO:
|
||||
m_FilterCoefTables.Tables02[1].Lo = _iValue;
|
||||
break;
|
||||
case VI_FILTER_COEF_2_HI:
|
||||
m_FilterCoefTables.Tables02[2].Hi = _iValue;
|
||||
break;
|
||||
case VI_FILTER_COEF_2_LO:
|
||||
m_FilterCoefTables.Tables02[2].Lo = _iValue;
|
||||
break;
|
||||
case VI_FILTER_COEF_3_HI:
|
||||
m_FilterCoefTables.Tables36[0].Hi = _iValue;
|
||||
break;
|
||||
case VI_FILTER_COEF_3_LO:
|
||||
m_FilterCoefTables.Tables36[0].Lo = _iValue;
|
||||
break;
|
||||
case VI_FILTER_COEF_4_HI:
|
||||
m_FilterCoefTables.Tables36[1].Hi = _iValue;
|
||||
break;
|
||||
case VI_FILTER_COEF_4_LO:
|
||||
m_FilterCoefTables.Tables36[1].Lo = _iValue;
|
||||
break;
|
||||
case VI_FILTER_COEF_5_HI:
|
||||
m_FilterCoefTables.Tables36[2].Hi = _iValue;
|
||||
break;
|
||||
case VI_FILTER_COEF_5_LO:
|
||||
m_FilterCoefTables.Tables36[2].Lo = _iValue;
|
||||
break;
|
||||
case VI_FILTER_COEF_6_HI:
|
||||
m_FilterCoefTables.Tables36[3].Hi = _iValue;
|
||||
break;
|
||||
case VI_FILTER_COEF_6_LO:
|
||||
m_FilterCoefTables.Tables36[3].Lo = _iValue;
|
||||
break;
|
||||
|
||||
case VI_UNK_AA_REG_HI:
|
||||
m_UnkAARegister = (m_UnkAARegister & 0x0000ffff) | (u32)(_iValue << 16);
|
||||
WARN_LOG(VIDEOINTERFACE, "(w16) to unknown AA register, not sure what it does :)");
|
||||
break;
|
||||
case VI_UNK_AA_REG_LO:
|
||||
m_UnkAARegister = (m_UnkAARegister & 0xffff0000) | _iValue;
|
||||
WARN_LOG(VIDEOINTERFACE, "(w16) to unknown AA register, not sure what it does :)");
|
||||
break;
|
||||
|
||||
case VI_CLOCK:
|
||||
m_Clock = _iValue;
|
||||
break;
|
||||
|
||||
case VI_DTV_STATUS:
|
||||
m_DTVStatus.Hex = _iValue;
|
||||
break;
|
||||
|
||||
case VI_FBWIDTH:
|
||||
m_FBWidth = _iValue;
|
||||
break;
|
||||
|
||||
case VI_BORDER_BLANK_END:
|
||||
m_BorderHBlank.Lo = _iValue;
|
||||
break;
|
||||
case VI_BORDER_BLANK_START:
|
||||
m_BorderHBlank.Hi = _iValue;
|
||||
break;
|
||||
|
||||
default:
|
||||
ERROR_LOG(VIDEOINTERFACE, "(w16) %04x to unknown register %x", _iValue, _iAddress & 0xfff);
|
||||
break;
|
||||
// Map 32 bit reads and writes to 16 bit reads and writes.
|
||||
for (int i = 0; i < 0x1000; i += 4)
|
||||
{
|
||||
mmio->Register(base | i,
|
||||
MMIO::ReadToSmaller<u32>(mmio, base | i, base | (i + 2)),
|
||||
MMIO::WriteToSmaller<u32>(mmio, base | i, base | (i + 2))
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
void SetRegionReg(char region)
|
||||
{
|
||||
if (!Core::g_CoreStartupParameter.bForceNTSCJ)
|
||||
m_DTVStatus.ntsc_j = region == 'J';
|
||||
}
|
||||
|
||||
void Read8(u8& _uReturnValue, const u32 _iAddress)
|
||||
{
|
||||
// HACK: Remove this function when the new MMIO interface is used.
|
||||
Memory::mmio_mapping->Read(_iAddress, _uReturnValue);
|
||||
}
|
||||
|
||||
void Read16(u16& _uReturnValue, const u32 _iAddress)
|
||||
{
|
||||
// HACK: Remove this function when the new MMIO interface is used.
|
||||
Memory::mmio_mapping->Read(_iAddress, _uReturnValue);
|
||||
}
|
||||
|
||||
void Write16(const u16 _iValue, const u32 _iAddress)
|
||||
{
|
||||
// HACK: Remove this function when the new MMIO interface is used.
|
||||
Memory::mmio_mapping->Write(_iAddress, _iValue);
|
||||
}
|
||||
|
||||
void Read32(u32& _uReturnValue, const u32 _iAddress)
|
||||
{
|
||||
u16 Hi = 0, Lo = 0;
|
||||
Read16(Hi, _iAddress);
|
||||
Read16(Lo, _iAddress + 2);
|
||||
_uReturnValue = (Hi << 16) | Lo;
|
||||
|
||||
INFO_LOG(VIDEOINTERFACE, "(r32): 0x%08x, 0x%08x", _uReturnValue, _iAddress);
|
||||
// HACK: Remove this function when the new MMIO interface is used.
|
||||
Memory::mmio_mapping->Read(_iAddress, _uReturnValue);
|
||||
}
|
||||
|
||||
void Write32(const u32 _iValue, const u32 _iAddress)
|
||||
{
|
||||
INFO_LOG(VIDEOINTERFACE, "(w32): 0x%08x, 0x%08x", _iValue, _iAddress);
|
||||
|
||||
// Allow 32-bit writes to the VI: although this is officially not
|
||||
// allowed, the hardware seems to accept it (for example, DesktopMan GC
|
||||
// Tetris uses it).
|
||||
Write16(_iValue >> 16, _iAddress);
|
||||
Write16(_iValue & 0xFFFF, _iAddress + 2);
|
||||
// HACK: Remove this function when the new MMIO interface is used.
|
||||
Memory::mmio_mapping->Write(_iAddress, _iValue);
|
||||
}
|
||||
|
||||
void UpdateInterrupts()
|
||||
|
|
|
|||
|
|
@ -5,7 +5,9 @@
|
|||
#pragma once
|
||||
|
||||
#include "CommonTypes.h"
|
||||
|
||||
class PointerWrap;
|
||||
namespace MMIO { class Mapping; }
|
||||
|
||||
namespace VideoInterface
|
||||
{
|
||||
|
|
@ -324,6 +326,8 @@ union UVIDTVStatus
|
|||
void SetRegionReg(char region);
|
||||
void DoState(PointerWrap &p);
|
||||
|
||||
void RegisterMMIO(MMIO::Mapping* mmio, u32 base);
|
||||
|
||||
void Read8(u8& _uReturnValue, const u32 _uAddress);
|
||||
void Read16(u16& _uReturnValue, const u32 _uAddress);
|
||||
void Read32(u32& _uReturnValue, const u32 _uAddress);
|
||||
|
|
|
|||
Loading…
Reference in New Issue