small build fix in debug mode, misc cleanup
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@1604 8ced0084-cf51-0410-be5f-012b33b47a6e
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@ -189,6 +189,7 @@ namespace CPUCompare
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jo.fpAccurateFlags = true;
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jo.optimizeGatherPipe = true;
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jo.fastInterrupts = false;
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jo.accurateSinglePrecision = true;
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gpr.SetEmitter(this);
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fpr.SetEmitter(this);
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@ -328,6 +329,9 @@ namespace CPUCompare
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if (emaddress == 0)
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PanicAlert("ERROR : Trying to compile at 0. LR=%08x", LR);
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// if (emaddress == 0x800aa278)
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// DebugBreak();
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int size;
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js.isLastInstruction = false;
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js.blockStart = emaddress;
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@ -433,6 +437,7 @@ namespace CPUCompare
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CALL(thunks.ProtectFunction((void *)&GPFifo::CheckGatherPipe, 0));
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}
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if (!ops[i].skip)
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PPCTables::CompileInstruction(ops[i].inst);
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gpr.SanityCheck();
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@ -19,6 +19,14 @@
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// See comments in Jit.cpp.
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// ========================
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// Mystery: Capcom vs SNK 800aa278
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// CR flags approach:
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// * Store that "N+Z flag contains CR0" or "S+Z flag contains CR3".
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// * All flag altering instructions flush this
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// * A flush simply does a conditional write to the appropriate CRx.
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// * If flag available, branch code can become absolutely trivial.
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#ifndef _JIT_H
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#define _JIT_H
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@ -128,6 +136,7 @@ private:
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bool enableFastMem;
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bool optimizeGatherPipe;
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bool fastInterrupts;
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bool accurateSinglePrecision;
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};
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@ -70,7 +70,6 @@ using namespace Gen;
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{
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LOG(DYNA_REC, "JIT Statistics =======================");
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LOG(DYNA_REC, "Number of blocks currently: %i", numBlocks);
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LOG(DYNA_REC, "Code cache size: %i b", GetCodePtr() - codeCache);
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LOG(DYNA_REC, "======================================");
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}
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@ -14,6 +14,7 @@
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// Official SVN repository and contact information can be found at
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// http://code.google.com/p/dolphin-emu/
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#include "../PowerPC.h"
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#include "../PPCTables.h"
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#include "../PPCAnalyst.h"
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@ -22,12 +23,9 @@
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#include "JitAsm.h"
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#include "JitRegCache.h"
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using namespace Gen;
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using namespace PowerPC;
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void RegCache::Start(PPCAnalyst::BlockRegStats &stats)
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{
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for (int i = 0; i < NUMXREGS; i++)
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@ -148,4 +148,3 @@
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};
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#endif
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@ -202,6 +202,7 @@
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if (!merge_branch) {
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// Keep the normal code separate for clarity.
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CMP(32, gpr.R(a), comparand);
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FixupBranch pLesser = J_CC(less_than);
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FixupBranch pGreater = J_CC(greater_than);
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MOV(8, M(&PowerPC::ppcState.cr_fast[crf]), Imm8(0x2)); // _x86Reg == 0
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@ -216,42 +217,45 @@
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} else {
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int test_bit = 8 >> (js.next_inst.BI & 3);
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bool condition = (js.next_inst.BO & 8) ? false : true;
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u32 destination;
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if (js.next_inst.AA)
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destination = SignExt16(js.next_inst.BD << 2);
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else
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destination = js.next_compilerPC + SignExt16(js.next_inst.BD << 2);
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CMP(32, gpr.R(a), comparand);
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gpr.UnlockAll();
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u32 destination1;
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if (js.next_inst.AA)
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destination1 = SignExt16(js.next_inst.BD << 2);
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else
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destination1 = js.next_compilerPC + SignExt16(js.next_inst.BD << 2);
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u32 destination2 = js.next_compilerPC + 4;
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// Test swapping (in the future, will be used to inline across branches the right way)
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// if (rand() & 1)
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// std::swap(destination1, destination2), condition = !condition;
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gpr.Flush(FLUSH_ALL);
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fpr.Flush(FLUSH_ALL);
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FixupBranch pLesser = J_CC(less_than);
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FixupBranch pGreater = J_CC(greater_than);
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MOV(8, M(&PowerPC::ppcState.cr_fast[crf]), Imm8(0x2)); // _x86Reg == 0
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MOV(8, M(&PowerPC::ppcState.cr_fast[crf]), Imm8(0x2)); // == 0
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FixupBranch continue1 = J();
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SetJumpTarget(pGreater);
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MOV(8, M(&PowerPC::ppcState.cr_fast[crf]), Imm8(0x4)); // _x86Reg > 0
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MOV(8, M(&PowerPC::ppcState.cr_fast[crf]), Imm8(0x4)); // > 0
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FixupBranch continue2 = J();
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SetJumpTarget(pLesser);
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MOV(8, M(&PowerPC::ppcState.cr_fast[crf]), Imm8(0x8)); // _x86Reg < 0
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MOV(8, M(&PowerPC::ppcState.cr_fast[crf]), Imm8(0x8)); // < 0
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FixupBranch continue3;
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if (!!(8 & test_bit) == condition) continue3 = J();
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//if (!!(8 & test_bit) != condition) SetJumpTarget(continue3);
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if (!!(4 & test_bit) != condition) SetJumpTarget(continue2);
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if (!!(2 & test_bit) != condition) SetJumpTarget(continue1);
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WriteExit(destination, 0);
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WriteExit(destination1, 0);
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if (!!(8 & test_bit) == condition) SetJumpTarget(continue3);
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if (!!(4 & test_bit) == condition) SetJumpTarget(continue2);
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if (!!(2 & test_bit) == condition) SetJumpTarget(continue1);
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WriteExit(js.next_compilerPC + 4, 1);
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WriteExit(destination2, 1);
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js.cancel = true;
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}
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@ -139,11 +139,18 @@ void Jit64::WriteFloatToConstRamAddress(const Gen::X64Reg& xmm_reg, u32 address)
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void Jit64::ForceSinglePrecisionS(X64Reg xmm) {
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// Most games don't need these. Zelda requires it though - some platforms get stuck without them.
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if (jo.accurateSinglePrecision)
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{
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CVTSD2SS(xmm, R(xmm));
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CVTSS2SD(xmm, R(xmm));
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}
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}
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void Jit64::ForceSinglePrecisionP(X64Reg xmm) {
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// Most games don't need these. Zelda requires it though - some platforms get stuck without them.
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if (jo.accurateSinglePrecision)
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{
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CVTPD2PS(xmm, R(xmm));
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CVTPS2PD(xmm, R(xmm));
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}
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}
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@ -313,6 +313,7 @@ bool Flatten(u32 address, int *realsize, BlockStats *st, BlockRegStats *gpa, Blo
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code[i].inst = inst;
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code[i].branchTo = -1;
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code[i].branchToIndex = -1;
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code[i].skip = false;
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GekkoOPInfo *opinfo = GetOpInfo(inst);
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if (opinfo)
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numCycles += opinfo->numCyclesMinusOne + 1;
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@ -345,6 +346,7 @@ bool Flatten(u32 address, int *realsize, BlockStats *st, BlockRegStats *gpa, Blo
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}
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else
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{
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code[i].skip = true;
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address = destination;
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}
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}
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@ -49,6 +49,7 @@ struct CodeOp //16B
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bool outputCR0;
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bool outputCR1;
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bool outputPS1;
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bool skip; // followed BL-s for example
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};
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struct BlockStats
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