Interpreter: Correct member variable casing

This commit is contained in:
Lioncash 2017-01-17 21:26:20 -05:00
parent e9b506638f
commit f0abdbdeb5
8 changed files with 71 additions and 71 deletions

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@ -30,41 +30,41 @@ namespace
u32 last_pc; u32 last_pc;
} }
bool Interpreter::m_EndBlock; bool Interpreter::m_end_block;
// function tables // function tables
Interpreter::Instruction Interpreter::m_opTable[64]; Interpreter::Instruction Interpreter::m_op_table[64];
Interpreter::Instruction Interpreter::m_opTable4[1024]; Interpreter::Instruction Interpreter::m_op_table4[1024];
Interpreter::Instruction Interpreter::m_opTable19[1024]; Interpreter::Instruction Interpreter::m_op_table19[1024];
Interpreter::Instruction Interpreter::m_opTable31[1024]; Interpreter::Instruction Interpreter::m_op_table31[1024];
Interpreter::Instruction Interpreter::m_opTable59[32]; Interpreter::Instruction Interpreter::m_op_table59[32];
Interpreter::Instruction Interpreter::m_opTable63[1024]; Interpreter::Instruction Interpreter::m_op_table63[1024];
void Interpreter::RunTable4(UGeckoInstruction _inst) void Interpreter::RunTable4(UGeckoInstruction _inst)
{ {
m_opTable4[_inst.SUBOP10](_inst); m_op_table4[_inst.SUBOP10](_inst);
} }
void Interpreter::RunTable19(UGeckoInstruction _inst) void Interpreter::RunTable19(UGeckoInstruction _inst)
{ {
m_opTable19[_inst.SUBOP10](_inst); m_op_table19[_inst.SUBOP10](_inst);
} }
void Interpreter::RunTable31(UGeckoInstruction _inst) void Interpreter::RunTable31(UGeckoInstruction _inst)
{ {
m_opTable31[_inst.SUBOP10](_inst); m_op_table31[_inst.SUBOP10](_inst);
} }
void Interpreter::RunTable59(UGeckoInstruction _inst) void Interpreter::RunTable59(UGeckoInstruction _inst)
{ {
m_opTable59[_inst.SUBOP5](_inst); m_op_table59[_inst.SUBOP5](_inst);
} }
void Interpreter::RunTable63(UGeckoInstruction _inst) void Interpreter::RunTable63(UGeckoInstruction _inst)
{ {
m_opTable63[_inst.SUBOP10](_inst); m_op_table63[_inst.SUBOP10](_inst);
} }
void Interpreter::Init() void Interpreter::Init()
{ {
g_bReserve = false; m_reserve = false;
m_EndBlock = false; m_end_block = false;
} }
void Interpreter::Shutdown() void Interpreter::Shutdown()
@ -153,11 +153,11 @@ int Interpreter::SingleStepInner()
UReg_MSR& msr = (UReg_MSR&)MSR; UReg_MSR& msr = (UReg_MSR&)MSR;
if (msr.FP) // If FPU is enabled, just execute if (msr.FP) // If FPU is enabled, just execute
{ {
m_opTable[instCode.OPCD](instCode); m_op_table[instCode.OPCD](instCode);
if (PowerPC::ppcState.Exceptions & EXCEPTION_DSI) if (PowerPC::ppcState.Exceptions & EXCEPTION_DSI)
{ {
PowerPC::CheckExceptions(); PowerPC::CheckExceptions();
m_EndBlock = true; m_end_block = true;
} }
} }
else else
@ -165,18 +165,18 @@ int Interpreter::SingleStepInner()
// check if we have to generate a FPU unavailable exception // check if we have to generate a FPU unavailable exception
if (!PPCTables::UsesFPU(instCode)) if (!PPCTables::UsesFPU(instCode))
{ {
m_opTable[instCode.OPCD](instCode); m_op_table[instCode.OPCD](instCode);
if (PowerPC::ppcState.Exceptions & EXCEPTION_DSI) if (PowerPC::ppcState.Exceptions & EXCEPTION_DSI)
{ {
PowerPC::CheckExceptions(); PowerPC::CheckExceptions();
m_EndBlock = true; m_end_block = true;
} }
} }
else else
{ {
PowerPC::ppcState.Exceptions |= EXCEPTION_FPU_UNAVAILABLE; PowerPC::ppcState.Exceptions |= EXCEPTION_FPU_UNAVAILABLE;
PowerPC::CheckExceptions(); PowerPC::CheckExceptions();
m_EndBlock = true; m_end_block = true;
} }
} }
} }
@ -184,7 +184,7 @@ int Interpreter::SingleStepInner()
{ {
// Memory exception on instruction fetch // Memory exception on instruction fetch
PowerPC::CheckExceptions(); PowerPC::CheckExceptions();
m_EndBlock = true; m_end_block = true;
} }
} }
last_pc = PC; last_pc = PC;
@ -243,9 +243,9 @@ void Interpreter::Run()
// JIT as possible. Does not take into account that some instructions take multiple cycles. // JIT as possible. Does not take into account that some instructions take multiple cycles.
while (PowerPC::ppcState.downcount > 0) while (PowerPC::ppcState.downcount > 0)
{ {
m_EndBlock = false; m_end_block = false;
int i; int i;
for (i = 0; !m_EndBlock; i++) for (i = 0; !m_end_block; i++)
{ {
#ifdef SHOW_HISTORY #ifdef SHOW_HISTORY
PCVec.push_back(PC); PCVec.push_back(PC);
@ -293,10 +293,10 @@ void Interpreter::Run()
// "fast" version of inner loop. well, it's not so fast. // "fast" version of inner loop. well, it's not so fast.
while (PowerPC::ppcState.downcount > 0) while (PowerPC::ppcState.downcount > 0)
{ {
m_EndBlock = false; m_end_block = false;
int cycles = 0; int cycles = 0;
while (!m_EndBlock) while (!m_end_block)
{ {
cycles += SingleStepInner(); cycles += SingleStepInner();
} }

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@ -261,12 +261,12 @@ public:
static void isync(UGeckoInstruction _inst); static void isync(UGeckoInstruction _inst);
using Instruction = void (*)(UGeckoInstruction instCode); using Instruction = void (*)(UGeckoInstruction instCode);
static Instruction m_opTable[64]; static Instruction m_op_table[64];
static Instruction m_opTable4[1024]; static Instruction m_op_table4[1024];
static Instruction m_opTable19[1024]; static Instruction m_op_table19[1024];
static Instruction m_opTable31[1024]; static Instruction m_op_table31[1024];
static Instruction m_opTable59[32]; static Instruction m_op_table59[32];
static Instruction m_opTable63[1024]; static Instruction m_op_table63[1024];
// singleton // singleton
static Interpreter* getInstance(); static Interpreter* getInstance();
@ -301,10 +301,10 @@ private:
static void Helper_FloatCompareOrdered(UGeckoInstruction _inst, double a, double b); static void Helper_FloatCompareOrdered(UGeckoInstruction _inst, double a, double b);
static void Helper_FloatCompareUnordered(UGeckoInstruction _inst, double a, double b); static void Helper_FloatCompareUnordered(UGeckoInstruction _inst, double a, double b);
static bool m_EndBlock; static bool m_end_block;
// TODO: These should really be in the save state, although it's unlikely to matter much. // TODO: These should really be in the save state, although it's unlikely to matter much.
// They are for lwarx and its friend stwcxd. // They are for lwarx and its friend stwcxd.
static bool g_bReserve; static bool m_reserve;
static u32 g_reserveAddr; static u32 m_reserve_address;
}; };

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@ -20,7 +20,7 @@ void Interpreter::bx(UGeckoInstruction _inst)
else else
NPC = PC + SignExt26(_inst.LI << 2); NPC = PC + SignExt26(_inst.LI << 2);
m_EndBlock = true; m_end_block = true;
if (NPC == PC) if (NPC == PC)
{ {
@ -52,7 +52,7 @@ void Interpreter::bcx(UGeckoInstruction _inst)
NPC = PC + SignExt16(_inst.BD << 2); NPC = PC + SignExt16(_inst.BD << 2);
} }
m_EndBlock = true; m_end_block = true;
// this code trys to detect the most common idle loop: // this code trys to detect the most common idle loop:
// lwz r0, XXXX(r13) // lwz r0, XXXX(r13)
@ -87,7 +87,7 @@ void Interpreter::bcctrx(UGeckoInstruction _inst)
LR = PC + 4; LR = PC + 4;
} }
m_EndBlock = true; m_end_block = true;
} }
void Interpreter::bclrx(UGeckoInstruction _inst) void Interpreter::bclrx(UGeckoInstruction _inst)
@ -105,12 +105,12 @@ void Interpreter::bclrx(UGeckoInstruction _inst)
LR = PC + 4; LR = PC + 4;
} }
m_EndBlock = true; m_end_block = true;
} }
void Interpreter::HLEFunction(UGeckoInstruction _inst) void Interpreter::HLEFunction(UGeckoInstruction _inst)
{ {
m_EndBlock = true; m_end_block = true;
HLE::Execute(PC, _inst.hex); HLE::Execute(PC, _inst.hex);
} }
@ -129,7 +129,7 @@ void Interpreter::rfi(UGeckoInstruction _inst)
// else // else
// set NPC to saved offset and resume // set NPC to saved offset and resume
NPC = SRR0; NPC = SRR0;
m_EndBlock = true; m_end_block = true;
} }
// sc isn't really used for anything important in GameCube games (just for a write barrier) so we // sc isn't really used for anything important in GameCube games (just for a write barrier) so we
@ -139,5 +139,5 @@ void Interpreter::sc(UGeckoInstruction _inst)
{ {
PowerPC::ppcState.Exceptions |= EXCEPTION_SYSCALL; PowerPC::ppcState.Exceptions |= EXCEPTION_SYSCALL;
PowerPC::CheckExceptions(); PowerPC::CheckExceptions();
m_EndBlock = true; m_end_block = true;
} }

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@ -157,7 +157,7 @@ void Interpreter::twi(UGeckoInstruction _inst)
{ {
PowerPC::ppcState.Exceptions |= EXCEPTION_PROGRAM; PowerPC::ppcState.Exceptions |= EXCEPTION_PROGRAM;
PowerPC::CheckExceptions(); PowerPC::CheckExceptions();
m_EndBlock = true; // Dunno about this m_end_block = true; // Dunno about this
} }
} }
@ -422,7 +422,7 @@ void Interpreter::tw(UGeckoInstruction _inst)
{ {
PowerPC::ppcState.Exceptions |= EXCEPTION_PROGRAM; PowerPC::ppcState.Exceptions |= EXCEPTION_PROGRAM;
PowerPC::CheckExceptions(); PowerPC::CheckExceptions();
m_EndBlock = true; // Dunno about this m_end_block = true; // Dunno about this
} }
} }

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@ -12,8 +12,8 @@
#include "Core/PowerPC/JitInterface.h" #include "Core/PowerPC/JitInterface.h"
#include "Core/PowerPC/PowerPC.h" #include "Core/PowerPC/PowerPC.h"
bool Interpreter::g_bReserve; bool Interpreter::m_reserve;
u32 Interpreter::g_reserveAddr; u32 Interpreter::m_reserve_address;
u32 Interpreter::Helper_Get_EA(const UGeckoInstruction _inst) u32 Interpreter::Helper_Get_EA(const UGeckoInstruction _inst)
{ {
@ -743,8 +743,8 @@ void Interpreter::lwarx(UGeckoInstruction _inst)
if (!(PowerPC::ppcState.Exceptions & EXCEPTION_DSI)) if (!(PowerPC::ppcState.Exceptions & EXCEPTION_DSI))
{ {
rGPR[_inst.RD] = temp; rGPR[_inst.RD] = temp;
g_bReserve = true; m_reserve = true;
g_reserveAddr = uAddress; m_reserve_address = uAddress;
} }
} }
@ -752,16 +752,16 @@ void Interpreter::stwcxd(UGeckoInstruction _inst)
{ {
// Stores Word Conditional indeXed // Stores Word Conditional indeXed
u32 uAddress; u32 uAddress;
if (g_bReserve) if (m_reserve)
{ {
uAddress = Helper_Get_EA_X(_inst); uAddress = Helper_Get_EA_X(_inst);
if (uAddress == g_reserveAddr) if (uAddress == m_reserve_address)
{ {
PowerPC::Write_U32(rGPR[_inst.RS], uAddress); PowerPC::Write_U32(rGPR[_inst.RS], uAddress);
if (!(PowerPC::ppcState.Exceptions & EXCEPTION_DSI)) if (!(PowerPC::ppcState.Exceptions & EXCEPTION_DSI))
{ {
g_bReserve = false; m_reserve = false;
SetCRField(0, 2 | GetXER_SO()); SetCRField(0, 2 | GetXER_SO());
return; return;
} }

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@ -166,7 +166,7 @@ void Interpreter::mtmsr(UGeckoInstruction _inst)
// Privileged? // Privileged?
MSR = rGPR[_inst.RS]; MSR = rGPR[_inst.RS];
PowerPC::CheckExceptions(); PowerPC::CheckExceptions();
m_EndBlock = true; m_end_block = true;
} }
// Segment registers. MMU control. // Segment registers. MMU control.

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@ -367,22 +367,22 @@ void InitTables()
// clear // clear
for (int i = 0; i < 64; i++) for (int i = 0; i < 64; i++)
{ {
Interpreter::m_opTable[i] = Interpreter::unknown_instruction; Interpreter::m_op_table[i] = Interpreter::unknown_instruction;
m_infoTable[i] = &unknownopinfo; m_infoTable[i] = &unknownopinfo;
} }
for (int i = 0; i < 32; i++) for (int i = 0; i < 32; i++)
{ {
Interpreter::m_opTable59[i] = Interpreter::unknown_instruction; Interpreter::m_op_table59[i] = Interpreter::unknown_instruction;
m_infoTable59[i] = &unknownopinfo; m_infoTable59[i] = &unknownopinfo;
} }
for (int i = 0; i < 1024; i++) for (int i = 0; i < 1024; i++)
{ {
Interpreter::m_opTable4[i] = Interpreter::unknown_instruction; Interpreter::m_op_table4[i] = Interpreter::unknown_instruction;
Interpreter::m_opTable19[i] = Interpreter::unknown_instruction; Interpreter::m_op_table19[i] = Interpreter::unknown_instruction;
Interpreter::m_opTable31[i] = Interpreter::unknown_instruction; Interpreter::m_op_table31[i] = Interpreter::unknown_instruction;
Interpreter::m_opTable63[i] = Interpreter::unknown_instruction; Interpreter::m_op_table63[i] = Interpreter::unknown_instruction;
m_infoTable4[i] = &unknownopinfo; m_infoTable4[i] = &unknownopinfo;
m_infoTable19[i] = &unknownopinfo; m_infoTable19[i] = &unknownopinfo;
m_infoTable31[i] = &unknownopinfo; m_infoTable31[i] = &unknownopinfo;
@ -391,7 +391,7 @@ void InitTables()
for (auto& tpl : primarytable) for (auto& tpl : primarytable)
{ {
Interpreter::m_opTable[tpl.opcode] = tpl.Inst; Interpreter::m_op_table[tpl.opcode] = tpl.Inst;
m_infoTable[tpl.opcode] = &tpl.opinfo; m_infoTable[tpl.opcode] = &tpl.opinfo;
} }
@ -401,7 +401,7 @@ void InitTables()
for (auto& tpl : table4_2) for (auto& tpl : table4_2)
{ {
int op = fill + tpl.opcode; int op = fill + tpl.opcode;
Interpreter::m_opTable4[op] = tpl.Inst; Interpreter::m_op_table4[op] = tpl.Inst;
m_infoTable4[op] = &tpl.opinfo; m_infoTable4[op] = &tpl.opinfo;
} }
} }
@ -412,7 +412,7 @@ void InitTables()
for (auto& tpl : table4_3) for (auto& tpl : table4_3)
{ {
int op = fill + tpl.opcode; int op = fill + tpl.opcode;
Interpreter::m_opTable4[op] = tpl.Inst; Interpreter::m_op_table4[op] = tpl.Inst;
m_infoTable4[op] = &tpl.opinfo; m_infoTable4[op] = &tpl.opinfo;
} }
} }
@ -420,35 +420,35 @@ void InitTables()
for (auto& tpl : table4) for (auto& tpl : table4)
{ {
int op = tpl.opcode; int op = tpl.opcode;
Interpreter::m_opTable4[op] = tpl.Inst; Interpreter::m_op_table4[op] = tpl.Inst;
m_infoTable4[op] = &tpl.opinfo; m_infoTable4[op] = &tpl.opinfo;
} }
for (auto& tpl : table31) for (auto& tpl : table31)
{ {
int op = tpl.opcode; int op = tpl.opcode;
Interpreter::m_opTable31[op] = tpl.Inst; Interpreter::m_op_table31[op] = tpl.Inst;
m_infoTable31[op] = &tpl.opinfo; m_infoTable31[op] = &tpl.opinfo;
} }
for (auto& tpl : table19) for (auto& tpl : table19)
{ {
int op = tpl.opcode; int op = tpl.opcode;
Interpreter::m_opTable19[op] = tpl.Inst; Interpreter::m_op_table19[op] = tpl.Inst;
m_infoTable19[op] = &tpl.opinfo; m_infoTable19[op] = &tpl.opinfo;
} }
for (auto& tpl : table59) for (auto& tpl : table59)
{ {
int op = tpl.opcode; int op = tpl.opcode;
Interpreter::m_opTable59[op] = tpl.Inst; Interpreter::m_op_table59[op] = tpl.Inst;
m_infoTable59[op] = &tpl.opinfo; m_infoTable59[op] = &tpl.opinfo;
} }
for (auto& tpl : table63) for (auto& tpl : table63)
{ {
int op = tpl.opcode; int op = tpl.opcode;
Interpreter::m_opTable63[op] = tpl.Inst; Interpreter::m_op_table63[op] = tpl.Inst;
m_infoTable63[op] = &tpl.opinfo; m_infoTable63[op] = &tpl.opinfo;
} }
@ -458,7 +458,7 @@ void InitTables()
for (auto& tpl : table63_2) for (auto& tpl : table63_2)
{ {
int op = fill + tpl.opcode; int op = fill + tpl.opcode;
Interpreter::m_opTable63[op] = tpl.Inst; Interpreter::m_op_table63[op] = tpl.Inst;
m_infoTable63[op] = &tpl.opinfo; m_infoTable63[op] = &tpl.opinfo;
} }
} }

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@ -74,15 +74,15 @@ Interpreter::Instruction GetInterpreterOp(UGeckoInstruction _inst)
switch (_inst.OPCD) switch (_inst.OPCD)
{ {
case 4: case 4:
return Interpreter::m_opTable4[_inst.SUBOP10]; return Interpreter::m_op_table4[_inst.SUBOP10];
case 19: case 19:
return Interpreter::m_opTable19[_inst.SUBOP10]; return Interpreter::m_op_table19[_inst.SUBOP10];
case 31: case 31:
return Interpreter::m_opTable31[_inst.SUBOP10]; return Interpreter::m_op_table31[_inst.SUBOP10];
case 59: case 59:
return Interpreter::m_opTable59[_inst.SUBOP5]; return Interpreter::m_op_table59[_inst.SUBOP5];
case 63: case 63:
return Interpreter::m_opTable63[_inst.SUBOP10]; return Interpreter::m_op_table63[_inst.SUBOP10];
default: default:
_assert_msg_(POWERPC, 0, "GetInterpreterOp - invalid subtable op %08x @ %08x", _inst.hex, PC); _assert_msg_(POWERPC, 0, "GetInterpreterOp - invalid subtable op %08x @ %08x", _inst.hex, PC);
return nullptr; return nullptr;
@ -95,7 +95,7 @@ Interpreter::Instruction GetInterpreterOp(UGeckoInstruction _inst)
_assert_msg_(POWERPC, 0, "GetInterpreterOp - invalid op %08x @ %08x", _inst.hex, PC); _assert_msg_(POWERPC, 0, "GetInterpreterOp - invalid op %08x @ %08x", _inst.hex, PC);
return nullptr; return nullptr;
} }
return Interpreter::m_opTable[_inst.OPCD]; return Interpreter::m_op_table[_inst.OPCD];
} }
} }
namespace PPCTables namespace PPCTables