parent
1e006b5b99
commit
efe8c75424
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@ -519,9 +519,8 @@ void BPWritten(const BPCmd& bp)
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for (u32 i = 0; i < tmem_cfg.preload_tile_info.count; ++i)
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for (u32 i = 0; i < tmem_cfg.preload_tile_info.count; ++i)
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{
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{
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// FIXME: Duplicate conditions.
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if (tmem_addr_even + TMEM_LINE_SIZE > TMEM_SIZE ||
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if (tmem_addr_even + TMEM_LINE_SIZE > TMEM_SIZE ||
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tmem_addr_even + TMEM_LINE_SIZE > TMEM_SIZE)
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tmem_addr_odd + TMEM_LINE_SIZE > TMEM_SIZE)
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break;
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break;
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memcpy(texMem + tmem_addr_even, src_ptr, TMEM_LINE_SIZE);
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memcpy(texMem + tmem_addr_even, src_ptr, TMEM_LINE_SIZE);
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@ -135,11 +135,10 @@ void SWBPWritten(int address, int newvalue)
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// AR and GB tiles are stored in separate TMEM banks => can't use a single memcpy for everything
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// AR and GB tiles are stored in separate TMEM banks => can't use a single memcpy for everything
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u32 tmem_addr_odd = tmem_cfg.preload_tmem_odd * TMEM_LINE_SIZE;
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u32 tmem_addr_odd = tmem_cfg.preload_tmem_odd * TMEM_LINE_SIZE;
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for (int i = 0; i < tmem_cfg.preload_tile_info.count; ++i)
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for (unsigned int i = 0; i < tmem_cfg.preload_tile_info.count; ++i)
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{
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{
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// FIXME: Duplicate conditions
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if (tmem_addr_even + TMEM_LINE_SIZE > TMEM_SIZE ||
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if (tmem_addr_even + TMEM_LINE_SIZE > TMEM_SIZE ||
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tmem_addr_even + TMEM_LINE_SIZE > TMEM_SIZE)
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tmem_addr_odd + TMEM_LINE_SIZE > TMEM_SIZE)
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break;
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break;
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memcpy(texMem + tmem_addr_even, src_ptr, TMEM_LINE_SIZE);
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memcpy(texMem + tmem_addr_even, src_ptr, TMEM_LINE_SIZE);
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