From efe20c93e839cdf5e378b8b77cda3146100e4bd8 Mon Sep 17 00:00:00 2001 From: skidau Date: Sat, 16 Jan 2010 04:43:07 +0000 Subject: [PATCH] In the Interpreter, marked mtmsr as an "end of block" instruction, making it consistent with the JIT tables. git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@4849 8ced0084-cf51-0410-be5f-012b33b47a6e --- .../Src/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Source/Core/Core/Src/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp b/Source/Core/Core/Src/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp index acf74ca0f9..3878723cce 100644 --- a/Source/Core/Core/Src/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp +++ b/Source/Core/Core/Src/PowerPC/Interpreter/Interpreter_SystemRegisters.cpp @@ -236,6 +236,7 @@ void mtmsr(UGeckoInstruction _inst) { // Privileged? MSR = m_GPR[_inst.RS]; + m_EndBlock = true; } // Segment registers. MMU control. @@ -264,8 +265,8 @@ void mtsrin(UGeckoInstruction _inst) void mftb(UGeckoInstruction _inst) { int iIndex = (_inst.TBR >> 5) | ((_inst.TBR & 0x1F) << 5); - if (iIndex == 268) m_GPR[_inst.RD] = TL; - else if (iIndex == 269) m_GPR[_inst.RD] = TU; + if (iIndex == SPR_TL) m_GPR[_inst.RD] = TL; + else if (iIndex == SPR_TU) m_GPR[_inst.RD] = TU; else _dbg_assert_(POWERPC, 0); }