From ef0e401708dc534e8bfac52e5e43086b4255c22d Mon Sep 17 00:00:00 2001
From: Scott Mansell <phiren@gmail.com>
Date: Sun, 12 Sep 2021 18:12:51 +1200
Subject: [PATCH] BPMem: Abstract TexUnit Addressing into struct

The addressing of the texture units is a bit non-obvious.
This struct abstracts the complexity away.
---
 Source/Core/VideoCommon/BPMemory.h    | 43 ++++++++++++++
 Source/Core/VideoCommon/BPStructs.cpp | 80 +++++++++++++--------------
 2 files changed, 83 insertions(+), 40 deletions(-)

diff --git a/Source/Core/VideoCommon/BPMemory.h b/Source/Core/VideoCommon/BPMemory.h
index a3cb28fc39..6c5b77220b 100644
--- a/Source/Core/VideoCommon/BPMemory.h
+++ b/Source/Core/VideoCommon/BPMemory.h
@@ -1979,6 +1979,49 @@ struct BPS_TmemConfig
   u32 texinvalidate;
 };
 
+// The addressing of the texture units is a bit non-obvious.
+// This struct abstracts the complexity away.
+union TexUnitAddress
+{
+  enum class Register : u32
+  {
+    SETMODE0 = 0,
+    SETMODE1 = 1,
+    SETIMAGE0 = 2,
+    SETIMAGE1 = 3,
+    SETIMAGE2 = 4,
+    SETIMAGE3 = 5,
+    SETTLUT = 6,
+    UNKNOWN = 7,
+  };
+
+  BitField<0, 2, u32> UnitIdLow;
+  BitField<2, 3, Register> Reg;
+  BitField<5, 1, u32> UnitIdHigh;
+
+  BitField<0, 6, u32> FullAddress;
+  u32 hex;
+
+  TexUnitAddress() : hex(0) {}
+  TexUnitAddress(u32 unit_id, Register reg = Register::SETMODE0) : hex(0)
+  {
+    UnitIdLow = unit_id & 3;
+    UnitIdHigh = unit_id >> 2;
+    Reg = reg;
+  }
+
+  static TexUnitAddress FromBPAddress(u32 Address)
+  {
+    TexUnitAddress Val;
+    // Clear upper two bits (which should always be 0x80)
+    Val.FullAddress = Address & 0x3f;
+    return Val;
+  }
+
+  u32 GetUnitID() const { return UnitIdLow | (UnitIdHigh << 2); }
+};
+static_assert(sizeof(TexUnitAddress) == sizeof(u32));
+
 // All of BP memory
 
 struct BPCmd
diff --git a/Source/Core/VideoCommon/BPStructs.cpp b/Source/Core/VideoCommon/BPStructs.cpp
index fb6372f09c..110ae5e803 100644
--- a/Source/Core/VideoCommon/BPStructs.cpp
+++ b/Source/Core/VideoCommon/BPStructs.cpp
@@ -646,48 +646,48 @@ static void BPWritten(const BPCmd& bp)
       GeometryShaderManager::SetTexCoordChanged((bp.address - BPMEM_SU_SSIZE) >> 1);
     }
     return;
-  // ------------------------
-  // BPMEM_TX_SETMODE0 - (Texture lookup and filtering mode) LOD/BIAS Clamp, MaxAnsio, LODBIAS,
-  // DiagLoad, Min Filter, Mag Filter, Wrap T, S
-  // BPMEM_TX_SETMODE1 - (LOD Stuff) - Max LOD, Min LOD
-  // ------------------------
-  case BPMEM_TX_SETMODE0:  // (0x90 for linear)
-  case BPMEM_TX_SETMODE0_4:
-    TextureCacheBase::InvalidateAllBindPoints();
-    return;
+  }
 
-  case BPMEM_TX_SETMODE1:
-  case BPMEM_TX_SETMODE1_4:
-    TextureCacheBase::InvalidateAllBindPoints();
-    return;
-  // --------------------------------------------
-  // BPMEM_TX_SETIMAGE0 - Texture width, height, format
-  // BPMEM_TX_SETIMAGE1 - even LOD address in TMEM - Image Type, Cache Height, Cache Width, TMEM
-  // Offset
-  // BPMEM_TX_SETIMAGE2 - odd LOD address in TMEM - Cache Height, Cache Width, TMEM Offset
-  // BPMEM_TX_SETIMAGE3 - Address of Texture in main memory
-  // --------------------------------------------
-  case BPMEM_TX_SETIMAGE0:
-  case BPMEM_TX_SETIMAGE0_4:
-  case BPMEM_TX_SETIMAGE1:
-  case BPMEM_TX_SETIMAGE1_4:
-  case BPMEM_TX_SETIMAGE2:
-  case BPMEM_TX_SETIMAGE2_4:
-  case BPMEM_TX_SETIMAGE3:
-  case BPMEM_TX_SETIMAGE3_4:
-    TextureCacheBase::InvalidateAllBindPoints();
-    return;
-  // -------------------------------
-  // Set a TLUT
-  // BPMEM_TX_SETTLUT - Format, TMEM Offset (offset of TLUT from start of TMEM high bank > > 5)
-  // -------------------------------
-  case BPMEM_TX_SETTLUT:
-  case BPMEM_TX_SETTLUT_4:
-    TextureCacheBase::InvalidateAllBindPoints();
-    return;
+  if ((bp.address & 0xc0) == 0x80)
+  {
+    auto tex_address = TexUnitAddress::FromBPAddress(bp.address);
 
-  default:
-    break;
+    switch (tex_address.Reg)
+    {
+    // ------------------------
+    // BPMEM_TX_SETMODE0 - (Texture lookup and filtering mode) LOD/BIAS Clamp, MaxAnsio, LODBIAS,
+    // DiagLoad, Min Filter, Mag Filter, Wrap T, S
+    // BPMEM_TX_SETMODE1 - (LOD Stuff) - Max LOD, Min LOD
+    // ------------------------
+    case TexUnitAddress::Register::SETMODE0:
+    case TexUnitAddress::Register::SETMODE1:
+      TextureCacheBase::InvalidateAllBindPoints();
+      return;
+
+    // --------------------------------------------
+    // BPMEM_TX_SETIMAGE0 - Texture width, height, format
+    // BPMEM_TX_SETIMAGE1 - even LOD address in TMEM - Image Type, Cache Height, Cache Width,
+    //                      TMEM Offset
+    // BPMEM_TX_SETIMAGE2 - odd LOD address in TMEM - Cache Height, Cache Width, TMEM Offset
+    // BPMEM_TX_SETIMAGE3 - Address of Texture in main memory
+    // --------------------------------------------
+    case TexUnitAddress::Register::SETIMAGE0:
+    case TexUnitAddress::Register::SETIMAGE1:
+    case TexUnitAddress::Register::SETIMAGE2:
+    case TexUnitAddress::Register::SETIMAGE3:
+      TextureCacheBase::InvalidateAllBindPoints();
+      return;
+
+    // -------------------------------
+    // Set a TLUT
+    // BPMEM_TX_SETTLUT - Format, TMEM Offset (offset of TLUT from start of TMEM high bank > > 5)
+    // -------------------------------
+    case TexUnitAddress::Register::SETTLUT:
+      TextureCacheBase::InvalidateAllBindPoints();
+      return;
+    case TexUnitAddress::Register::UNKNOWN:
+      break;  // Not handled
+    }
   }
 
   switch (bp.address & 0xF0)