Add phire's more accurate DoubleToSingle version
This method doesn't involve messing around with the quirks of the x87 FPU and should be reasonably fast. As a bonus, it does the correct thing for out-of-range doubles. However, it is also a little slower and only benefits programs that rely on undefined behavior so it is disabled for now.
This commit is contained in:
Tillmann Karras
parent
7062cf8657
commit
ee21cbe2d1
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@ -234,9 +234,9 @@ inline u32 ConvertToSingleFTZ(u64 x)
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inline u64 ConvertToDouble(u32 _x)
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{
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// This is a little-endian re-implementation of the algrothm described in
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// the Power PC Programming Enviroments Manual for Loading single
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// percision floating point numbers.
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// This is a little-endian re-implementation of the algorithm described in
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// the PowerPC Programming Environments Manual for loading single
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// precision floating point numbers.
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// See page 566 of http://www.freescale.com/files/product/doc/MPCFPE32B.pdf
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u64 x = _x;
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@ -438,12 +438,142 @@ static const __uint128_t GC_ALIGNED16(double_qnan_bit) = 0x0008000000000000;
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static const __uint128_t GC_ALIGNED16(double_exponent) = 0x7ff0000000000000;
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#endif
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// Since the following two functions are used in non-arithmetic PPC float instructions,
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// Since the following float conversion functions are used in non-arithmetic PPC float instructions,
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// they must convert floats bitexact and never flush denormals to zero or turn SNaNs into QNaNs.
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// This means we can't use CVTSS2SD/CVTSD2SS :(
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// The x87 FPU doesn't even support flush-to-zero so we can use FLD+FSTP even on denormals.
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// If the number is a NaN, make sure to set the QNaN bit back to its original value.
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// Another problem is that officially, converting doubles to single format results in undefined behavior.
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// Relying on undefined behavior is a bug so no software should ever do this.
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// In case it does happen, phire's more accurate implementation of ConvertDoubleToSingle() is reproduced below.
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//#define MORE_ACCURATE_DOUBLETOSINGLE
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#ifdef MORE_ACCURATE_DOUBLETOSINGLE
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#ifdef _WIN32
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#ifdef _M_X64
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static const __m128i GC_ALIGNED16(double_fraction) = _mm_set_epi64x(0, 0x000fffffffffffff);
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static const __m128i GC_ALIGNED16(double_sign_bit) = _mm_set_epi64x(0, 0x8000000000000000);
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static const __m128i GC_ALIGNED16(double_explicit_top_bit) = _mm_set_epi64x(0, 0x0010000000000000);
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static const __m128i GC_ALIGNED16(double_top_two_bits) = _mm_set_epi64x(0, 0xc000000000000000);
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static const __m128i GC_ALIGNED16(double_bottom_bits) = _mm_set_epi64x(0, 0x07ffffffe0000000);
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#else
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static const __m128i GC_ALIGNED16(double_fraction) = _mm_set_epi32(0, 0, 0x000fffff, 0xffffffff);
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static const __m128i GC_ALIGNED16(double_sign_bit) = _mm_set_epi32(0, 0, 0x80000000, 0x00000000);
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static const __m128i GC_ALIGNED16(double_explicit_top_bit) = _mm_set_epi32(0, 0, 0x00100000, 0x00000000);
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static const __m128i GC_ALIGNED16(double_top_two_bits) = _mm_set_epi32(0, 0, 0xc0000000, 0x00000000);
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static const __m128i GC_ALIGNED16(double_bottom_bits) = _mm_set_epi32(0, 0, 0x07ffffff, 0xe0000000);
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#endif
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#else
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static const __uint128_t GC_ALIGNED16(double_fraction) = 0x000fffffffffffff;
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static const __uint128_t GC_ALIGNED16(double_sign_bit) = 0x8000000000000000;
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static const __uint128_t GC_ALIGNED16(double_explicit_top_bit) = 0x0010000000000000;
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static const __uint128_t GC_ALIGNED16(double_top_two_bits) = 0xc000000000000000;
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static const __uint128_t GC_ALIGNED16(double_bottom_bits) = 0x07ffffffe0000000;
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#endif
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// This is the same algorithm used in the interpreter (and actual hardware)
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// The documentation states that the conversion of a double with an outside the
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// valid range for a single (or a single denormal) is undefined.
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// But testing on actual hardware shows it always picks bits 0..1 and 5..34
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// unless the exponent is in the range of 874 to 896.
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void EmuCodeBlock::ConvertDoubleToSingle(X64Reg dst, X64Reg src)
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{
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MOVSD(XMM1, R(src));
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// Grab Exponent
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PAND(XMM1, M((void *)&double_exponent));
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PSRLQ(XMM1, 52);
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MOVD_xmm(R(EAX), XMM1);
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// Check if the double is in the range of valid single subnormal
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CMP(16, R(EAX), Imm16(896));
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FixupBranch NoDenormalize = J_CC(CC_G);
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CMP(16, R(EAX), Imm16(874));
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FixupBranch NoDenormalize2 = J_CC(CC_L);
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// Denormalise
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// shift = (905 - Exponent) plus the 21 bit double to single shift
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MOV(16, R(EAX), Imm16(905 + 21));
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MOVD_xmm(XMM0, R(EAX));
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PSUBQ(XMM0, R(XMM1));
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// xmm1 = fraction | 0x0010000000000000
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MOVSD(XMM1, R(src));
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PAND(XMM1, M((void *)&double_fraction));
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POR(XMM1, M((void *)&double_explicit_top_bit));
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// fraction >> shift
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PSRLQ(XMM1, R(XMM0));
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// OR the sign bit in.
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MOVSD(XMM0, R(src));
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PAND(XMM0, M((void *)&double_sign_bit));
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PSRLQ(XMM0, 32);
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POR(XMM1, R(XMM0));
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FixupBranch end = J(false); // Goto end
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SetJumpTarget(NoDenormalize);
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SetJumpTarget(NoDenormalize2);
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// Don't Denormalize
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// We want bits 0, 1
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MOVSD(XMM1, R(src));
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PAND(XMM1, M((void *)&double_top_two_bits));
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PSRLQ(XMM1, 32);
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// And 5 through to 34
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MOVSD(XMM0, R(src));
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PAND(XMM0, M((void *)&double_bottom_bits));
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PSRLQ(XMM0, 29);
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// OR them togther
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POR(XMM1, R(XMM0));
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// End
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SetJumpTarget(end);
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MOVDDUP(dst, R(XMM1));
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}
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#else // MORE_ACCURATE_DOUBLETOSINGLE
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void EmuCodeBlock::ConvertDoubleToSingle(X64Reg dst, X64Reg src)
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{
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MOVSD(M(&temp64), src);
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MOVSD(XMM1, R(src));
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FLD(64, M(&temp64));
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CCFlags cond;
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if (cpu_info.bSSE4_1) {
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PTEST(XMM1, M((void *)&double_exponent));
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cond = CC_NC;
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} else {
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FNSTSW_AX();
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TEST(16, R(AX), Imm16(x87_InvalidOperation));
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cond = CC_Z;
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}
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FSTP(32, M(&temp32));
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MOVSS(XMM0, M(&temp32));
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FixupBranch dont_reset_qnan_bit = J_CC(cond);
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PANDN(XMM1, M((void *)&double_qnan_bit));
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PSRLQ(XMM1, 29);
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if (cpu_info.bAVX) {
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VPANDN(XMM0, XMM1, R(XMM0));
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} else {
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PANDN(XMM1, R(XMM0));
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MOVSS(XMM0, R(XMM1));
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}
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SetJumpTarget(dont_reset_qnan_bit);
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MOVDDUP(dst, R(XMM0));
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}
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#endif // MORE_ACCURATE_DOUBLETOSINGLE
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void EmuCodeBlock::ConvertSingleToDouble(X64Reg dst, X64Reg src, bool src_is_gpr)
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{
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if (src_is_gpr) {
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@ -480,37 +610,6 @@ void EmuCodeBlock::ConvertSingleToDouble(X64Reg dst, X64Reg src, bool src_is_gpr
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MOVDDUP(dst, R(dst));
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}
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void EmuCodeBlock::ConvertDoubleToSingle(X64Reg dst, X64Reg src)
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{
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MOVSD(M(&temp64), src);
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MOVSD(XMM1, R(src));
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FLD(64, M(&temp64));
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CCFlags cond;
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if (cpu_info.bSSE4_1) {
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PTEST(XMM1, M((void *)&double_exponent));
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cond = CC_NC;
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} else {
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FNSTSW_AX();
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TEST(16, R(AX), Imm16(x87_InvalidOperation));
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cond = CC_Z;
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}
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FSTP(32, M(&temp32));
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MOVSS(XMM0, M(&temp32));
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FixupBranch dont_reset_qnan_bit = J_CC(cond);
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PANDN(XMM1, M((void *)&double_qnan_bit));
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PSRLQ(XMM1, 29);
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if (cpu_info.bAVX) {
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VPANDN(XMM0, XMM1, R(XMM0));
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} else {
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PANDN(XMM1, R(XMM0));
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MOVSS(XMM0, R(XMM1));
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}
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SetJumpTarget(dont_reset_qnan_bit);
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MOVDDUP(dst, R(XMM0));
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}
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void EmuCodeBlock::JitClearCA()
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{
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AND(32, M(&PowerPC::ppcState.spr[SPR_XER]), Imm32(~XER_CA_MASK)); //XER.CA = 0
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