PowerPC: Pass on full 32-bit register contents for 8/16-bit writes
This commit is contained in:
JosJuice
parent
c56526d5f8
commit
ecbce0a204
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@ -323,14 +323,14 @@ void Interpreter::lwzu(UGeckoInstruction inst)
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void Interpreter::stb(UGeckoInstruction inst)
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{
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PowerPC::Write_U8((u8)rGPR[inst.RS], Helper_Get_EA(PowerPC::ppcState, inst));
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PowerPC::Write_U8(rGPR[inst.RS], Helper_Get_EA(PowerPC::ppcState, inst));
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}
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void Interpreter::stbu(UGeckoInstruction inst)
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{
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const u32 address = Helper_Get_EA_U(PowerPC::ppcState, inst);
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PowerPC::Write_U8((u8)rGPR[inst.RS], address);
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PowerPC::Write_U8(rGPR[inst.RS], address);
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if (!(PowerPC::ppcState.Exceptions & EXCEPTION_DSI))
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{
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rGPR[inst.RA] = address;
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@ -399,14 +399,14 @@ void Interpreter::stfsu(UGeckoInstruction inst)
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void Interpreter::sth(UGeckoInstruction inst)
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{
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PowerPC::Write_U16((u16)rGPR[inst.RS], Helper_Get_EA(PowerPC::ppcState, inst));
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PowerPC::Write_U16(rGPR[inst.RS], Helper_Get_EA(PowerPC::ppcState, inst));
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}
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void Interpreter::sthu(UGeckoInstruction inst)
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{
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const u32 address = Helper_Get_EA_U(PowerPC::ppcState, inst);
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PowerPC::Write_U16((u16)rGPR[inst.RS], address);
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PowerPC::Write_U16(rGPR[inst.RS], address);
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if (!(PowerPC::ppcState.Exceptions & EXCEPTION_DSI))
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{
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rGPR[inst.RA] = address;
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@ -731,7 +731,7 @@ void Interpreter::stbux(UGeckoInstruction inst)
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{
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const u32 address = Helper_Get_EA_UX(PowerPC::ppcState, inst);
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PowerPC::Write_U8((u8)rGPR[inst.RS], address);
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PowerPC::Write_U8(rGPR[inst.RS], address);
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if (!(PowerPC::ppcState.Exceptions & EXCEPTION_DSI))
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{
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rGPR[inst.RA] = address;
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@ -740,7 +740,7 @@ void Interpreter::stbux(UGeckoInstruction inst)
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void Interpreter::stbx(UGeckoInstruction inst)
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{
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PowerPC::Write_U8((u8)rGPR[inst.RS], Helper_Get_EA_X(PowerPC::ppcState, inst));
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PowerPC::Write_U8(rGPR[inst.RS], Helper_Get_EA_X(PowerPC::ppcState, inst));
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}
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void Interpreter::stfdux(UGeckoInstruction inst)
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@ -819,14 +819,14 @@ void Interpreter::stfsx(UGeckoInstruction inst)
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void Interpreter::sthbrx(UGeckoInstruction inst)
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{
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PowerPC::Write_U16(Common::swap16((u16)rGPR[inst.RS]), Helper_Get_EA_X(PowerPC::ppcState, inst));
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PowerPC::Write_U16_Swap(rGPR[inst.RS], Helper_Get_EA_X(PowerPC::ppcState, inst));
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}
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void Interpreter::sthux(UGeckoInstruction inst)
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{
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const u32 address = Helper_Get_EA_UX(PowerPC::ppcState, inst);
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PowerPC::Write_U16((u16)rGPR[inst.RS], address);
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PowerPC::Write_U16(rGPR[inst.RS], address);
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if (!(PowerPC::ppcState.Exceptions & EXCEPTION_DSI))
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{
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rGPR[inst.RA] = address;
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@ -835,7 +835,7 @@ void Interpreter::sthux(UGeckoInstruction inst)
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void Interpreter::sthx(UGeckoInstruction inst)
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{
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PowerPC::Write_U16((u16)rGPR[inst.RS], Helper_Get_EA_X(PowerPC::ppcState, inst));
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PowerPC::Write_U16(rGPR[inst.RS], Helper_Get_EA_X(PowerPC::ppcState, inst));
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}
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// lswi - bizarro string instruction
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@ -968,7 +968,7 @@ void Interpreter::stwbrx(UGeckoInstruction inst)
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{
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const u32 address = Helper_Get_EA_X(PowerPC::ppcState, inst);
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PowerPC::Write_U32(Common::swap32(rGPR[inst.RS]), address);
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PowerPC::Write_U32_Swap(rGPR[inst.RS], address);
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}
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// The following two instructions are for SMP communications. On a single
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@ -8,6 +8,7 @@
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#include <cstring>
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#include <string>
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#include "Common/Assert.h"
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#include "Common/BitUtils.h"
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#include "Common/CommonTypes.h"
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@ -256,9 +257,26 @@ static T ReadFromHardware(u32 em_address)
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return 0;
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}
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template <XCheckTLBFlag flag, typename T, bool never_translate = false>
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static void WriteToHardware(u32 em_address, const T data)
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template <XCheckTLBFlag flag, bool never_translate = false>
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static void WriteToHardware(u32 em_address, const u32 data, const u32 size)
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{
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DEBUG_ASSERT(size <= 4);
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const u32 em_address_start_page = em_address & ~(HW_PAGE_SIZE - 1);
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const u32 em_address_end_page = (em_address + size - 1) & ~(HW_PAGE_SIZE - 1);
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if (em_address_start_page != em_address_end_page)
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{
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// The write crosses a page boundary. Break it up into two writes.
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// TODO: floats on non-word-aligned boundaries should technically cause alignment exceptions.
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// Note that "word" means 32-bit, so paired singles or doubles might still be 32-bit aligned!
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const u32 first_half_size = em_address_end_page - em_address;
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const u32 second_half_size = size - first_half_size;
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WriteToHardware<flag, never_translate>(
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em_address, Common::RotateRight(data, second_half_size * 8), first_half_size);
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WriteToHardware<flag, never_translate>(em_address_end_page, data, second_half_size);
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return;
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}
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if (!never_translate && MSR.DR)
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{
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auto translated_addr = TranslateAddress<flag>(em_address);
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@ -268,51 +286,24 @@ static void WriteToHardware(u32 em_address, const T data)
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GenerateDSIException(em_address, true);
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return;
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}
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if ((em_address & (sizeof(T) - 1)) &&
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(em_address & (HW_PAGE_SIZE - 1)) > HW_PAGE_SIZE - sizeof(T))
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{
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// This could be unaligned down to the byte level... hopefully this is rare, so doing it this
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// way isn't too terrible.
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// TODO: floats on non-word-aligned boundaries should technically cause alignment exceptions.
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// Note that "word" means 32-bit, so paired singles or doubles might still be 32-bit aligned!
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u32 em_address_next_page = (em_address + sizeof(T) - 1) & ~(HW_PAGE_SIZE - 1);
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auto addr_next_page = TranslateAddress<flag>(em_address_next_page);
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if (!addr_next_page.Success())
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{
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if (flag == XCheckTLBFlag::Write)
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GenerateDSIException(em_address_next_page, true);
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return;
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}
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T val = bswap(data);
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u32 addr_translated = translated_addr.address;
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for (size_t i = 0; i < sizeof(T); i++, addr_translated++)
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{
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if (em_address + i == em_address_next_page)
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addr_translated = addr_next_page.address;
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WriteToHardware<flag, u8, true>(addr_translated, static_cast<u8>(val >> (i * 8)));
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}
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return;
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}
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em_address = translated_addr.address;
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}
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// TODO: Make sure these are safe for unaligned addresses.
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const u32 swapped_data = Common::swap32(Common::RotateRight(data, size * 8));
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if (Memory::m_pRAM && (em_address & 0xF8000000) == 0x00000000)
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{
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// Handle RAM; the masking intentionally discards bits (essentially creating
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// mirrors of memory).
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// TODO: Only the first GetRamSizeReal() is supposed to be backed by actual memory.
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const T swapped_data = bswap(data);
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std::memcpy(&Memory::m_pRAM[em_address & Memory::GetRamMask()], &swapped_data, sizeof(T));
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std::memcpy(&Memory::m_pRAM[em_address & Memory::GetRamMask()], &swapped_data, size);
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return;
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}
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if (Memory::m_pEXRAM && (em_address >> 28) == 0x1 &&
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(em_address & 0x0FFFFFFF) < Memory::GetExRamSizeReal())
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{
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const T swapped_data = bswap(data);
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std::memcpy(&Memory::m_pEXRAM[em_address & 0x0FFFFFFF], &swapped_data, sizeof(T));
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std::memcpy(&Memory::m_pEXRAM[em_address & 0x0FFFFFFF], &swapped_data, size);
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return;
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}
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@ -320,8 +311,7 @@ static void WriteToHardware(u32 em_address, const T data)
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if (Memory::m_pL1Cache && (em_address >> 28 == 0xE) &&
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(em_address < (0xE0000000 + Memory::GetL1CacheSize())))
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{
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const T swapped_data = bswap(data);
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std::memcpy(&Memory::m_pL1Cache[em_address & 0x0FFFFFFF], &swapped_data, sizeof(T));
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std::memcpy(&Memory::m_pL1Cache[em_address & 0x0FFFFFFF], &swapped_data, size);
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return;
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}
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@ -330,9 +320,7 @@ static void WriteToHardware(u32 em_address, const T data)
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// [0x7E000000, 0x80000000).
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if (Memory::m_pFakeVMEM && ((em_address & 0xFE000000) == 0x7E000000))
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{
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const T swapped_data = bswap(data);
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std::memcpy(&Memory::m_pFakeVMEM[em_address & Memory::GetFakeVMemMask()], &swapped_data,
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sizeof(T));
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std::memcpy(&Memory::m_pFakeVMEM[em_address & Memory::GetFakeVMemMask()], &swapped_data, size);
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return;
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}
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@ -341,19 +329,24 @@ static void WriteToHardware(u32 em_address, const T data)
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// Pac-Man World 3 in particular is affected by this.
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if (flag == XCheckTLBFlag::Write && (em_address & 0xFFFFF000) == 0x0C008000)
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{
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switch (sizeof(T))
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switch (size)
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{
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case 1:
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GPFifo::Write8((u8)data);
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GPFifo::Write8(static_cast<u8>(data));
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return;
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case 2:
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GPFifo::Write16((u16)data);
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GPFifo::Write16(static_cast<u16>(data));
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return;
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case 4:
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GPFifo::Write32((u32)data);
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GPFifo::Write32(data);
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return;
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case 8:
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GPFifo::Write64((u64)data);
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default:
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// Some kind of misaligned write. TODO: Does this match how the actual hardware handles it?
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for (size_t i = size * 8; i > 0;)
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{
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i -= 8;
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GPFifo::Write8(static_cast<u8>(data >> i));
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}
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return;
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}
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}
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@ -362,12 +355,28 @@ static void WriteToHardware(u32 em_address, const T data)
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{
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if (em_address < 0x0c000000)
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{
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EFB_Write((u32)data, em_address);
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EFB_Write(data, em_address);
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return;
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}
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else
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switch (size)
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{
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Memory::mmio_mapping->Write(em_address, data);
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case 1:
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Memory::mmio_mapping->Write<u8>(em_address, static_cast<u8>(data));
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return;
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case 2:
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Memory::mmio_mapping->Write<u16>(em_address, static_cast<u16>(data));
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return;
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case 4:
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Memory::mmio_mapping->Write<u32>(em_address, data);
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return;
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default:
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// Some kind of misaligned write. TODO: Does this match how the actual hardware handles it?
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for (size_t i = size * 8; i > 0; em_address++)
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{
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i -= 8;
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Memory::mmio_mapping->Write<u8>(em_address, static_cast<u8>(data >> i));
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}
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return;
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}
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}
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@ -608,42 +617,40 @@ u32 Read_U16_ZX(const u32 address)
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return Read_U16(address);
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}
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void Write_U8(const u8 var, const u32 address)
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void Write_U8(const u32 var, const u32 address)
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{
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Memcheck(address, var, true, 1);
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WriteToHardware<XCheckTLBFlag::Write, u8>(address, var);
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WriteToHardware<XCheckTLBFlag::Write>(address, var, 1);
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}
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void Write_U16(const u16 var, const u32 address)
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void Write_U16(const u32 var, const u32 address)
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{
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Memcheck(address, var, true, 2);
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WriteToHardware<XCheckTLBFlag::Write, u16>(address, var);
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WriteToHardware<XCheckTLBFlag::Write>(address, var, 2);
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}
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void Write_U16_Swap(const u16 var, const u32 address)
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void Write_U16_Swap(const u32 var, const u32 address)
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{
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Memcheck(address, var, true, 2);
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Write_U16(Common::swap16(var), address);
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Write_U16((var & 0xFFFF0000) | Common::swap16(static_cast<u16>(var)), address);
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}
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void Write_U32(const u32 var, const u32 address)
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{
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Memcheck(address, var, true, 4);
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WriteToHardware<XCheckTLBFlag::Write, u32>(address, var);
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WriteToHardware<XCheckTLBFlag::Write>(address, var, 4);
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}
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void Write_U32_Swap(const u32 var, const u32 address)
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{
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Memcheck(address, var, true, 4);
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Write_U32(Common::swap32(var), address);
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}
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void Write_U64(const u64 var, const u32 address)
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{
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Memcheck(address, (u32)var, true, 8);
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WriteToHardware<XCheckTLBFlag::Write, u64>(address, var);
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WriteToHardware<XCheckTLBFlag::Write>(address, static_cast<u32>(var >> 32), 4);
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WriteToHardware<XCheckTLBFlag::Write>(address + sizeof(u32), static_cast<u32>(var), 4);
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}
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void Write_U64_Swap(const u64 var, const u32 address)
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{
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Memcheck(address, (u32)var, true, 8);
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Write_U64(Common::swap64(var), address);
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}
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@ -688,24 +695,25 @@ double HostRead_F64(const u32 address)
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return Common::BitCast<double>(integral);
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}
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void HostWrite_U8(const u8 var, const u32 address)
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void HostWrite_U8(const u32 var, const u32 address)
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{
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WriteToHardware<XCheckTLBFlag::NoException, u8>(address, var);
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WriteToHardware<XCheckTLBFlag::NoException>(address, var, 1);
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}
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void HostWrite_U16(const u16 var, const u32 address)
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void HostWrite_U16(const u32 var, const u32 address)
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{
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WriteToHardware<XCheckTLBFlag::NoException, u16>(address, var);
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WriteToHardware<XCheckTLBFlag::NoException>(address, var, 2);
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}
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void HostWrite_U32(const u32 var, const u32 address)
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{
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WriteToHardware<XCheckTLBFlag::NoException, u32>(address, var);
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WriteToHardware<XCheckTLBFlag::NoException>(address, var, 4);
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}
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void HostWrite_U64(const u64 var, const u32 address)
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{
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WriteToHardware<XCheckTLBFlag::NoException, u64>(address, var);
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WriteToHardware<XCheckTLBFlag::NoException>(address, static_cast<u32>(var >> 32), 4);
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WriteToHardware<XCheckTLBFlag::NoException>(address + sizeof(u32), static_cast<u32>(var), 4);
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}
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void HostWrite_F32(const float var, const u32 address)
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@ -722,8 +730,8 @@ void HostWrite_F64(const double var, const u32 address)
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HostWrite_U64(integral, address);
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}
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template <typename T>
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static TryWriteResult HostTryWriteUX(const T var, const u32 address, RequestedAddressSpace space)
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static TryWriteResult HostTryWriteUX(const u32 var, const u32 address, const u32 size,
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RequestedAddressSpace space)
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{
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if (!HostIsRAMAddress(address, space))
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return TryWriteResult();
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@ -731,15 +739,15 @@ static TryWriteResult HostTryWriteUX(const T var, const u32 address, RequestedAd
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switch (space)
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{
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case RequestedAddressSpace::Effective:
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WriteToHardware<XCheckTLBFlag::NoException, T>(address, var);
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WriteToHardware<XCheckTLBFlag::NoException>(address, var, size);
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return TryWriteResult(!!MSR.DR);
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case RequestedAddressSpace::Physical:
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WriteToHardware<XCheckTLBFlag::NoException, T, true>(address, var);
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WriteToHardware<XCheckTLBFlag::NoException, true>(address, var, size);
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return TryWriteResult(false);
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case RequestedAddressSpace::Virtual:
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if (!MSR.DR)
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return TryWriteResult();
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WriteToHardware<XCheckTLBFlag::NoException, T>(address, var);
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WriteToHardware<XCheckTLBFlag::NoException>(address, var, size);
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return TryWriteResult(true);
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}
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@ -747,24 +755,28 @@ static TryWriteResult HostTryWriteUX(const T var, const u32 address, RequestedAd
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return TryWriteResult();
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}
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TryWriteResult HostTryWriteU8(const u8 var, const u32 address, RequestedAddressSpace space)
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TryWriteResult HostTryWriteU8(const u32 var, const u32 address, RequestedAddressSpace space)
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{
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return HostTryWriteUX<u8>(var, address, space);
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return HostTryWriteUX(var, address, 1, space);
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}
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TryWriteResult HostTryWriteU16(const u16 var, const u32 address, RequestedAddressSpace space)
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TryWriteResult HostTryWriteU16(const u32 var, const u32 address, RequestedAddressSpace space)
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{
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return HostTryWriteUX<u16>(var, address, space);
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return HostTryWriteUX(var, address, 2, space);
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}
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TryWriteResult HostTryWriteU32(const u32 var, const u32 address, RequestedAddressSpace space)
|
||||
{
|
||||
return HostTryWriteUX<u32>(var, address, space);
|
||||
return HostTryWriteUX(var, address, 4, space);
|
||||
}
|
||||
|
||||
TryWriteResult HostTryWriteU64(const u64 var, const u32 address, RequestedAddressSpace space)
|
||||
{
|
||||
return HostTryWriteUX<u64>(var, address, space);
|
||||
const TryWriteResult result = HostTryWriteUX(static_cast<u32>(var >> 32), address, 4, space);
|
||||
if (!result)
|
||||
return result;
|
||||
|
||||
return HostTryWriteUX(static_cast<u32>(var), address + 4, 4, space);
|
||||
}
|
||||
|
||||
TryWriteResult HostTryWriteF32(const float var, const u32 address, RequestedAddressSpace space)
|
||||
|
|
@ -1001,8 +1013,8 @@ void ClearCacheLine(u32 address)
|
|||
|
||||
// TODO: This isn't precisely correct for non-RAM regions, but the difference
|
||||
// is unlikely to matter.
|
||||
for (u32 i = 0; i < 32; i += 8)
|
||||
WriteToHardware<XCheckTLBFlag::Write, u64, true>(address + i, 0);
|
||||
for (u32 i = 0; i < 32; i += 4)
|
||||
WriteToHardware<XCheckTLBFlag::Write, true>(address + i, 0, 4);
|
||||
}
|
||||
|
||||
u32 IsOptimizableMMIOAccess(u32 address, u32 access_size)
|
||||
|
|
|
|||
|
|
@ -86,8 +86,8 @@ HostTryReadString(u32 address, size_t size = 0,
|
|||
// Writes a value to emulated memory using the currently active MMU settings.
|
||||
// If the write fails (eg. address does not correspond to a mapped address in the current address
|
||||
// space), a PanicAlert will be shown to the user.
|
||||
void HostWrite_U8(u8 var, u32 address);
|
||||
void HostWrite_U16(u16 var, u32 address);
|
||||
void HostWrite_U8(u32 var, u32 address);
|
||||
void HostWrite_U16(u32 var, u32 address);
|
||||
void HostWrite_U32(u32 var, u32 address);
|
||||
void HostWrite_U64(u64 var, u32 address);
|
||||
void HostWrite_F32(float var, u32 address);
|
||||
|
|
@ -111,9 +111,9 @@ struct TryWriteResult
|
|||
// If the write succeeds, the returned TryWriteResult contains information on whether the given
|
||||
// address had to be translated or not. Unlike the HostWrite functions, this does not raise a
|
||||
// user-visible alert on failure.
|
||||
TryWriteResult HostTryWriteU8(u8 var, const u32 address,
|
||||
TryWriteResult HostTryWriteU8(u32 var, const u32 address,
|
||||
RequestedAddressSpace space = RequestedAddressSpace::Effective);
|
||||
TryWriteResult HostTryWriteU16(u16 var, const u32 address,
|
||||
TryWriteResult HostTryWriteU16(u32 var, const u32 address,
|
||||
RequestedAddressSpace space = RequestedAddressSpace::Effective);
|
||||
TryWriteResult HostTryWriteU32(u32 var, const u32 address,
|
||||
RequestedAddressSpace space = RequestedAddressSpace::Effective);
|
||||
|
|
@ -158,12 +158,12 @@ double Read_F64(u32 address);
|
|||
u32 Read_U8_ZX(u32 address);
|
||||
u32 Read_U16_ZX(u32 address);
|
||||
|
||||
void Write_U8(u8 var, u32 address);
|
||||
void Write_U16(u16 var, u32 address);
|
||||
void Write_U8(u32 var, u32 address);
|
||||
void Write_U16(u32 var, u32 address);
|
||||
void Write_U32(u32 var, u32 address);
|
||||
void Write_U64(u64 var, u32 address);
|
||||
|
||||
void Write_U16_Swap(u16 var, u32 address);
|
||||
void Write_U16_Swap(u32 var, u32 address);
|
||||
void Write_U32_Swap(u32 var, u32 address);
|
||||
void Write_U64_Swap(u64 var, u32 address);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue