VideoCommon/PixelEngine: Refactor to class, move to Core::System.
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parent
82e87cf7b9
commit
ec8aaf1f30
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@ -50,7 +50,7 @@ void MemoryManager::InitMMIO(bool is_wii)
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auto& system = Core::System::GetInstance();
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auto& system = Core::System::GetInstance();
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system.GetCommandProcessor().RegisterMMIO(system, m_mmio_mapping.get(), 0x0C000000);
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system.GetCommandProcessor().RegisterMMIO(system, m_mmio_mapping.get(), 0x0C000000);
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PixelEngine::RegisterMMIO(m_mmio_mapping.get(), 0x0C001000);
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system.GetPixelEngine().RegisterMMIO(m_mmio_mapping.get(), 0x0C001000);
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VideoInterface::RegisterMMIO(m_mmio_mapping.get(), 0x0C002000);
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VideoInterface::RegisterMMIO(m_mmio_mapping.get(), 0x0C002000);
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ProcessorInterface::RegisterMMIO(m_mmio_mapping.get(), 0x0C003000);
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ProcessorInterface::RegisterMMIO(m_mmio_mapping.get(), 0x0C003000);
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MemoryInterface::RegisterMMIO(m_mmio_mapping.get(), 0x0C004000);
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MemoryInterface::RegisterMMIO(m_mmio_mapping.get(), 0x0C004000);
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@ -20,6 +20,7 @@
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#include "Core/HW/VideoInterface.h"
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#include "Core/HW/VideoInterface.h"
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#include "VideoCommon/CommandProcessor.h"
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#include "VideoCommon/CommandProcessor.h"
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#include "VideoCommon/Fifo.h"
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#include "VideoCommon/Fifo.h"
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#include "VideoCommon/PixelEngine.h"
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namespace Core
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namespace Core
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{
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{
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@ -39,6 +40,7 @@ struct System::Impl
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Fifo::FifoManager m_fifo;
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Fifo::FifoManager m_fifo;
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Memory::MemoryManager m_memory;
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Memory::MemoryManager m_memory;
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MemoryInterface::MemoryInterfaceState m_memory_interface_state;
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MemoryInterface::MemoryInterfaceState m_memory_interface_state;
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PixelEngine::PixelEngineManager m_pixel_engine;
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SerialInterface::SerialInterfaceState m_serial_interface_state;
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SerialInterface::SerialInterfaceState m_serial_interface_state;
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Sram m_sram;
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Sram m_sram;
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VideoInterface::VideoInterfaceState m_video_interface_state;
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VideoInterface::VideoInterfaceState m_video_interface_state;
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@ -137,6 +139,11 @@ MemoryInterface::MemoryInterfaceState& System::GetMemoryInterfaceState() const
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return m_impl->m_memory_interface_state;
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return m_impl->m_memory_interface_state;
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}
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}
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PixelEngine::PixelEngineManager& System::GetPixelEngine() const
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{
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return m_impl->m_pixel_engine;
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}
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SerialInterface::SerialInterfaceState& System::GetSerialInterfaceState() const
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SerialInterface::SerialInterfaceState& System::GetSerialInterfaceState() const
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{
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{
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return m_impl->m_serial_interface_state;
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return m_impl->m_serial_interface_state;
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@ -48,6 +48,10 @@ namespace MemoryInterface
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{
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{
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class MemoryInterfaceState;
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class MemoryInterfaceState;
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};
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};
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namespace PixelEngine
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{
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class PixelEngineManager;
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};
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namespace SerialInterface
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namespace SerialInterface
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{
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{
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class SerialInterfaceState;
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class SerialInterfaceState;
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@ -101,6 +105,7 @@ public:
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Fifo::FifoManager& GetFifo() const;
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Fifo::FifoManager& GetFifo() const;
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Memory::MemoryManager& GetMemory() const;
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Memory::MemoryManager& GetMemory() const;
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MemoryInterface::MemoryInterfaceState& GetMemoryInterfaceState() const;
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MemoryInterface::MemoryInterfaceState& GetMemoryInterfaceState() const;
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PixelEngine::PixelEngineManager& GetPixelEngine() const;
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SerialInterface::SerialInterfaceState& GetSerialInterfaceState() const;
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SerialInterface::SerialInterfaceState& GetSerialInterfaceState() const;
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Sram& GetSRAM() const;
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Sram& GetSRAM() const;
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VideoInterface::VideoInterfaceState& GetVideoInterfaceState() const;
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VideoInterface::VideoInterfaceState& GetVideoInterfaceState() const;
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@ -9,6 +9,7 @@
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#include "Common/GL/GLContext.h"
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#include "Common/GL/GLContext.h"
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#include "Core/HW/Memmap.h"
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#include "Core/HW/Memmap.h"
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#include "Core/System.h"
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#include "VideoBackends/Software/EfbCopy.h"
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#include "VideoBackends/Software/EfbCopy.h"
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#include "VideoBackends/Software/EfbInterface.h"
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#include "VideoBackends/Software/EfbInterface.h"
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@ -136,7 +137,8 @@ u32 SWRenderer::AccessEFB(EFBAccessType type, u32 x, u32 y, u32 InputData)
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value = (color >> 8) | (color & 0xff) << 24;
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value = (color >> 8) | (color & 0xff) << 24;
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// check what to do with the alpha channel (GX_PokeAlphaRead)
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// check what to do with the alpha channel (GX_PokeAlphaRead)
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PixelEngine::AlphaReadMode alpha_read_mode = PixelEngine::GetAlphaReadMode();
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PixelEngine::AlphaReadMode alpha_read_mode =
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Core::System::GetInstance().GetPixelEngine().GetAlphaReadMode();
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if (alpha_read_mode == PixelEngine::AlphaReadMode::ReadNone)
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if (alpha_read_mode == PixelEngine::AlphaReadMode::ReadNone)
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{
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{
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@ -186,7 +186,7 @@ static void BPWritten(const BPCmd& bp, int cycles_into_future)
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g_framebuffer_manager->RefreshPeekCache();
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g_framebuffer_manager->RefreshPeekCache();
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auto& system = Core::System::GetInstance();
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auto& system = Core::System::GetInstance();
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if (!system.GetFifo().UseDeterministicGPUThread())
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if (!system.GetFifo().UseDeterministicGPUThread())
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PixelEngine::SetFinish(cycles_into_future); // may generate interrupt
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system.GetPixelEngine().SetFinish(cycles_into_future); // may generate interrupt
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DEBUG_LOG_FMT(VIDEO, "GXSetDrawDone SetPEFinish (value: {:#04X})", bp.newvalue & 0xFFFF);
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DEBUG_LOG_FMT(VIDEO, "GXSetDrawDone SetPEFinish (value: {:#04X})", bp.newvalue & 0xFFFF);
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return;
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return;
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}
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}
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@ -204,7 +204,10 @@ static void BPWritten(const BPCmd& bp, int cycles_into_future)
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g_framebuffer_manager->RefreshPeekCache();
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g_framebuffer_manager->RefreshPeekCache();
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auto& system = Core::System::GetInstance();
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auto& system = Core::System::GetInstance();
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if (!system.GetFifo().UseDeterministicGPUThread())
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if (!system.GetFifo().UseDeterministicGPUThread())
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PixelEngine::SetToken(static_cast<u16>(bp.newvalue & 0xFFFF), false, cycles_into_future);
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{
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system.GetPixelEngine().SetToken(static_cast<u16>(bp.newvalue & 0xFFFF), false,
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cycles_into_future);
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}
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DEBUG_LOG_FMT(VIDEO, "SetPEToken {:#06X}", bp.newvalue & 0xFFFF);
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DEBUG_LOG_FMT(VIDEO, "SetPEToken {:#06X}", bp.newvalue & 0xFFFF);
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return;
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return;
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}
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}
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@ -216,7 +219,10 @@ static void BPWritten(const BPCmd& bp, int cycles_into_future)
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g_framebuffer_manager->RefreshPeekCache();
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g_framebuffer_manager->RefreshPeekCache();
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auto& system = Core::System::GetInstance();
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auto& system = Core::System::GetInstance();
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if (!system.GetFifo().UseDeterministicGPUThread())
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if (!system.GetFifo().UseDeterministicGPUThread())
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PixelEngine::SetToken(static_cast<u16>(bp.newvalue & 0xFFFF), true, cycles_into_future);
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{
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system.GetPixelEngine().SetToken(static_cast<u16>(bp.newvalue & 0xFFFF), true,
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cycles_into_future);
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}
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DEBUG_LOG_FMT(VIDEO, "SetPEToken + INT {:#06X}", bp.newvalue & 0xFFFF);
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DEBUG_LOG_FMT(VIDEO, "SetPEToken + INT {:#06X}", bp.newvalue & 0xFFFF);
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return;
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return;
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}
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}
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@ -764,13 +770,15 @@ void LoadBPRegPreprocess(u8 reg, u32 value, int cycles_into_future)
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{
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{
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case BPMEM_SETDRAWDONE:
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case BPMEM_SETDRAWDONE:
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if ((newval & 0xff) == 0x02)
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if ((newval & 0xff) == 0x02)
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PixelEngine::SetFinish(cycles_into_future);
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Core::System::GetInstance().GetPixelEngine().SetFinish(cycles_into_future);
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break;
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break;
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case BPMEM_PE_TOKEN_ID:
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case BPMEM_PE_TOKEN_ID:
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PixelEngine::SetToken(newval & 0xffff, false, cycles_into_future);
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Core::System::GetInstance().GetPixelEngine().SetToken(newval & 0xffff, false,
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cycles_into_future);
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break;
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break;
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case BPMEM_PE_TOKEN_INT_ID: // Pixel Engine Interrupt Token ID
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case BPMEM_PE_TOKEN_INT_ID: // Pixel Engine Interrupt Token ID
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PixelEngine::SetToken(newval & 0xffff, true, cycles_into_future);
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Core::System::GetInstance().GetPixelEngine().SetToken(newval & 0xffff, true,
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cycles_into_future);
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break;
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break;
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}
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}
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}
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}
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@ -25,188 +25,54 @@
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namespace PixelEngine
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namespace PixelEngine
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{
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{
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// Note: These enums are (assumed to be) identical to the one in BPMemory, but the base type is set
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// to u16 instead of u32 for BitField
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enum class CompareMode : u16
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{
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Never = 0,
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Less = 1,
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Equal = 2,
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LEqual = 3,
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Greater = 4,
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NEqual = 5,
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GEqual = 6,
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Always = 7
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};
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union UPEZConfReg
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{
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u16 hex;
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BitField<0, 1, bool, u16> z_comparator_enable;
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BitField<1, 3, CompareMode, u16> function;
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BitField<4, 1, bool, u16> z_update_enable;
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};
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enum class SrcBlendFactor : u16
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{
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Zero = 0,
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One = 1,
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DstClr = 2,
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InvDstClr = 3,
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SrcAlpha = 4,
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InvSrcAlpha = 5,
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DstAlpha = 6,
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InvDstAlpha = 7
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};
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enum class DstBlendFactor : u16
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{
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Zero = 0,
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One = 1,
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SrcClr = 2,
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InvSrcClr = 3,
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SrcAlpha = 4,
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InvSrcAlpha = 5,
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DstAlpha = 6,
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InvDstAlpha = 7
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};
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enum class LogicOp : u16
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{
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Clear = 0,
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And = 1,
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AndReverse = 2,
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Copy = 3,
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AndInverted = 4,
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NoOp = 5,
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Xor = 6,
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Or = 7,
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Nor = 8,
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Equiv = 9,
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Invert = 10,
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OrReverse = 11,
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CopyInverted = 12,
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OrInverted = 13,
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Nand = 14,
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Set = 15
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};
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union UPEAlphaConfReg
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{
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u16 hex;
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BitField<0, 1, bool, u16> blend; // Set for GX_BM_BLEND or GX_BM_SUBTRACT
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BitField<1, 1, bool, u16> logic; // Set for GX_BM_LOGIC
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BitField<2, 1, bool, u16> dither;
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BitField<3, 1, bool, u16> color_update_enable;
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BitField<4, 1, bool, u16> alpha_update_enable;
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BitField<5, 3, DstBlendFactor, u16> dst_factor;
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BitField<8, 3, SrcBlendFactor, u16> src_factor;
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BitField<11, 1, bool, u16> subtract; // Set for GX_BM_SUBTRACT
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BitField<12, 4, LogicOp, u16> logic_op;
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};
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union UPEDstAlphaConfReg
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{
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u16 hex;
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BitField<0, 8, u8, u16> alpha;
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BitField<8, 1, bool, u16> enable;
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};
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union UPEAlphaModeConfReg
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{
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u16 hex;
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BitField<0, 8, u8, u16> threshold;
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// Yagcd and libogc use 8 bits for this, but the enum only needs 3
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BitField<8, 3, CompareMode, u16> compare_mode;
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};
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union UPEAlphaReadReg
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{
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u16 hex;
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BitField<0, 2, AlphaReadMode, u16> read_mode;
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};
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// fifo Control Register
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union UPECtrlReg
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{
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u16 hex;
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BitField<0, 1, bool, u16> pe_token_enable;
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BitField<1, 1, bool, u16> pe_finish_enable;
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BitField<2, 1, bool, u16> pe_token; // Write only
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BitField<3, 1, bool, u16> pe_finish; // Write only
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};
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// STATE_TO_SAVE
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static UPEZConfReg m_ZConf;
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static UPEAlphaConfReg m_AlphaConf;
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static UPEDstAlphaConfReg m_DstAlphaConf;
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static UPEAlphaModeConfReg m_AlphaModeConf;
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static UPEAlphaReadReg m_AlphaRead;
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static UPECtrlReg m_Control;
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static std::mutex s_token_finish_mutex;
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static u16 s_token;
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static u16 s_token_pending;
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static bool s_token_interrupt_pending;
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static bool s_finish_interrupt_pending;
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static bool s_event_raised;
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static bool s_signal_token_interrupt;
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static bool s_signal_finish_interrupt;
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static CoreTiming::EventType* et_SetTokenFinishOnMainThread;
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enum
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enum
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{
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{
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INT_CAUSE_PE_TOKEN = 0x200, // GP Token
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INT_CAUSE_PE_TOKEN = 0x200, // GP Token
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INT_CAUSE_PE_FINISH = 0x400, // GP Finished
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INT_CAUSE_PE_FINISH = 0x400, // GP Finished
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};
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};
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void DoState(PointerWrap& p)
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void PixelEngineManager::DoState(PointerWrap& p)
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{
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{
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p.Do(m_ZConf);
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p.Do(m_z_conf);
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p.Do(m_AlphaConf);
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p.Do(m_alpha_conf);
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p.Do(m_DstAlphaConf);
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p.Do(m_dst_alpha_conf);
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p.Do(m_AlphaModeConf);
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p.Do(m_alpha_mode_conf);
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p.Do(m_AlphaRead);
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p.Do(m_alpha_read);
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p.Do(m_Control);
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p.Do(m_control);
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p.Do(s_token);
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p.Do(m_token);
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p.Do(s_token_pending);
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p.Do(m_token_pending);
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p.Do(s_token_interrupt_pending);
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p.Do(m_token_interrupt_pending);
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p.Do(s_finish_interrupt_pending);
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p.Do(m_finish_interrupt_pending);
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p.Do(s_event_raised);
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p.Do(m_event_raised);
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p.Do(s_signal_token_interrupt);
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p.Do(m_signal_token_interrupt);
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p.Do(s_signal_finish_interrupt);
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p.Do(m_signal_finish_interrupt);
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}
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}
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static void UpdateInterrupts();
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void PixelEngineManager::Init()
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static void SetTokenFinish_OnMainThread(Core::System& system, u64 userdata, s64 cyclesLate);
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void Init()
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{
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{
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m_Control.hex = 0;
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m_control.hex = 0;
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m_ZConf.hex = 0;
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m_z_conf.hex = 0;
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m_AlphaConf.hex = 0;
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m_alpha_conf.hex = 0;
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m_DstAlphaConf.hex = 0;
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m_dst_alpha_conf.hex = 0;
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m_AlphaModeConf.hex = 0;
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m_alpha_mode_conf.hex = 0;
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m_AlphaRead.hex = 0;
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m_alpha_read.hex = 0;
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s_token = 0;
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m_token = 0;
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s_token_pending = 0;
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m_token_pending = 0;
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s_token_interrupt_pending = false;
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m_token_interrupt_pending = false;
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s_finish_interrupt_pending = false;
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m_finish_interrupt_pending = false;
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s_event_raised = false;
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m_event_raised = false;
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s_signal_token_interrupt = false;
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m_signal_token_interrupt = false;
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s_signal_finish_interrupt = false;
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m_signal_finish_interrupt = false;
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et_SetTokenFinishOnMainThread = Core::System::GetInstance().GetCoreTiming().RegisterEvent(
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m_event_type_set_token_finish = Core::System::GetInstance().GetCoreTiming().RegisterEvent(
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"SetTokenFinish", SetTokenFinish_OnMainThread);
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"SetTokenFinish", SetTokenFinish_OnMainThread_Static);
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}
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}
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void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
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void PixelEngineManager::RegisterMMIO(MMIO::Mapping* mmio, u32 base)
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{
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{
|
||||||
// Directly mapped registers.
|
// Directly mapped registers.
|
||||||
struct
|
struct
|
||||||
|
@ -214,11 +80,11 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
|
||||||
u32 addr;
|
u32 addr;
|
||||||
u16* ptr;
|
u16* ptr;
|
||||||
} directly_mapped_vars[] = {
|
} directly_mapped_vars[] = {
|
||||||
{PE_ZCONF, &m_ZConf.hex},
|
{PE_ZCONF, &m_z_conf.hex},
|
||||||
{PE_ALPHACONF, &m_AlphaConf.hex},
|
{PE_ALPHACONF, &m_alpha_conf.hex},
|
||||||
{PE_DSTALPHACONF, &m_DstAlphaConf.hex},
|
{PE_DSTALPHACONF, &m_dst_alpha_conf.hex},
|
||||||
{PE_ALPHAMODE, &m_AlphaModeConf.hex},
|
{PE_ALPHAMODE, &m_alpha_mode_conf.hex},
|
||||||
{PE_ALPHAREAD, &m_AlphaRead.hex},
|
{PE_ALPHAREAD, &m_alpha_read.hex},
|
||||||
};
|
};
|
||||||
for (auto& mapped_var : directly_mapped_vars)
|
for (auto& mapped_var : directly_mapped_vars)
|
||||||
{
|
{
|
||||||
|
@ -253,27 +119,29 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
|
||||||
}
|
}
|
||||||
|
|
||||||
// Control register
|
// Control register
|
||||||
mmio->Register(base | PE_CTRL_REGISTER, MMIO::DirectRead<u16>(&m_Control.hex),
|
mmio->Register(base | PE_CTRL_REGISTER, MMIO::DirectRead<u16>(&m_control.hex),
|
||||||
MMIO::ComplexWrite<u16>([](Core::System&, u32, u16 val) {
|
MMIO::ComplexWrite<u16>([](Core::System& system, u32, u16 val) {
|
||||||
|
auto& pe = system.GetPixelEngine();
|
||||||
|
|
||||||
UPECtrlReg tmpCtrl{.hex = val};
|
UPECtrlReg tmpCtrl{.hex = val};
|
||||||
|
|
||||||
if (tmpCtrl.pe_token)
|
if (tmpCtrl.pe_token)
|
||||||
s_signal_token_interrupt = false;
|
pe.m_signal_token_interrupt = false;
|
||||||
|
|
||||||
if (tmpCtrl.pe_finish)
|
if (tmpCtrl.pe_finish)
|
||||||
s_signal_finish_interrupt = false;
|
pe.m_signal_finish_interrupt = false;
|
||||||
|
|
||||||
m_Control.pe_token_enable = tmpCtrl.pe_token_enable.Value();
|
pe.m_control.pe_token_enable = tmpCtrl.pe_token_enable.Value();
|
||||||
m_Control.pe_finish_enable = tmpCtrl.pe_finish_enable.Value();
|
pe.m_control.pe_finish_enable = tmpCtrl.pe_finish_enable.Value();
|
||||||
m_Control.pe_token = false; // this flag is write only
|
pe.m_control.pe_token = false; // this flag is write only
|
||||||
m_Control.pe_finish = false; // this flag is write only
|
pe.m_control.pe_finish = false; // this flag is write only
|
||||||
|
|
||||||
DEBUG_LOG_FMT(PIXELENGINE, "(w16) CTRL_REGISTER: {:#06x}", val);
|
DEBUG_LOG_FMT(PIXELENGINE, "(w16) CTRL_REGISTER: {:#06x}", val);
|
||||||
UpdateInterrupts();
|
pe.UpdateInterrupts();
|
||||||
}));
|
}));
|
||||||
|
|
||||||
// Token register, readonly.
|
// Token register, readonly.
|
||||||
mmio->Register(base | PE_TOKEN_REG, MMIO::DirectRead<u16>(&s_token), MMIO::InvalidWrite<u16>());
|
mmio->Register(base | PE_TOKEN_REG, MMIO::DirectRead<u16>(&m_token), MMIO::InvalidWrite<u16>());
|
||||||
|
|
||||||
// BBOX registers, readonly and need to update a flag.
|
// BBOX registers, readonly and need to update a flag.
|
||||||
for (int i = 0; i < 4; ++i)
|
for (int i = 0; i < 4; ++i)
|
||||||
|
@ -286,35 +154,42 @@ void RegisterMMIO(MMIO::Mapping* mmio, u32 base)
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static void UpdateInterrupts()
|
void PixelEngineManager::UpdateInterrupts()
|
||||||
{
|
{
|
||||||
// check if there is a token-interrupt
|
// check if there is a token-interrupt
|
||||||
ProcessorInterface::SetInterrupt(INT_CAUSE_PE_TOKEN,
|
ProcessorInterface::SetInterrupt(INT_CAUSE_PE_TOKEN,
|
||||||
s_signal_token_interrupt && m_Control.pe_token_enable);
|
m_signal_token_interrupt && m_control.pe_token_enable);
|
||||||
|
|
||||||
// check if there is a finish-interrupt
|
// check if there is a finish-interrupt
|
||||||
ProcessorInterface::SetInterrupt(INT_CAUSE_PE_FINISH,
|
ProcessorInterface::SetInterrupt(INT_CAUSE_PE_FINISH,
|
||||||
s_signal_finish_interrupt && m_Control.pe_finish_enable);
|
m_signal_finish_interrupt && m_control.pe_finish_enable);
|
||||||
}
|
}
|
||||||
|
|
||||||
static void SetTokenFinish_OnMainThread(Core::System& system, u64 userdata, s64 cyclesLate)
|
void PixelEngineManager::SetTokenFinish_OnMainThread_Static(Core::System& system, u64 userdata,
|
||||||
|
s64 cycles_late)
|
||||||
{
|
{
|
||||||
std::unique_lock<std::mutex> lk(s_token_finish_mutex);
|
system.GetPixelEngine().SetTokenFinish_OnMainThread(system, userdata, cycles_late);
|
||||||
s_event_raised = false;
|
}
|
||||||
|
|
||||||
s_token = s_token_pending;
|
void PixelEngineManager::SetTokenFinish_OnMainThread(Core::System& system, u64 userdata,
|
||||||
|
s64 cycles_late)
|
||||||
|
{
|
||||||
|
std::unique_lock<std::mutex> lk(m_token_finish_mutex);
|
||||||
|
m_event_raised = false;
|
||||||
|
|
||||||
if (s_token_interrupt_pending)
|
m_token = m_token_pending;
|
||||||
|
|
||||||
|
if (m_token_interrupt_pending)
|
||||||
{
|
{
|
||||||
s_token_interrupt_pending = false;
|
m_token_interrupt_pending = false;
|
||||||
s_signal_token_interrupt = true;
|
m_signal_token_interrupt = true;
|
||||||
UpdateInterrupts();
|
UpdateInterrupts();
|
||||||
}
|
}
|
||||||
|
|
||||||
if (s_finish_interrupt_pending)
|
if (m_finish_interrupt_pending)
|
||||||
{
|
{
|
||||||
s_finish_interrupt_pending = false;
|
m_finish_interrupt_pending = false;
|
||||||
s_signal_finish_interrupt = true;
|
m_signal_finish_interrupt = true;
|
||||||
UpdateInterrupts();
|
UpdateInterrupts();
|
||||||
lk.unlock();
|
lk.unlock();
|
||||||
Core::FrameUpdateOnCPUThread();
|
Core::FrameUpdateOnCPUThread();
|
||||||
|
@ -322,14 +197,14 @@ static void SetTokenFinish_OnMainThread(Core::System& system, u64 userdata, s64
|
||||||
}
|
}
|
||||||
|
|
||||||
// Raise the event handler above on the CPU thread.
|
// Raise the event handler above on the CPU thread.
|
||||||
// s_token_finish_mutex must be locked.
|
// m_token_finish_mutex must be locked.
|
||||||
// THIS IS EXECUTED FROM VIDEO THREAD
|
// THIS IS EXECUTED FROM VIDEO THREAD
|
||||||
static void RaiseEvent(int cycles_into_future)
|
void PixelEngineManager::RaiseEvent(int cycles_into_future)
|
||||||
{
|
{
|
||||||
if (s_event_raised)
|
if (m_event_raised)
|
||||||
return;
|
return;
|
||||||
|
|
||||||
s_event_raised = true;
|
m_event_raised = true;
|
||||||
|
|
||||||
CoreTiming::FromThread from = CoreTiming::FromThread::NON_CPU;
|
CoreTiming::FromThread from = CoreTiming::FromThread::NON_CPU;
|
||||||
s64 cycles = 0; // we don't care about timings for dual core mode.
|
s64 cycles = 0; // we don't care about timings for dual core mode.
|
||||||
|
@ -342,40 +217,35 @@ static void RaiseEvent(int cycles_into_future)
|
||||||
// games time to setup any interrupt state
|
// games time to setup any interrupt state
|
||||||
cycles = std::max(500, cycles_into_future);
|
cycles = std::max(500, cycles_into_future);
|
||||||
}
|
}
|
||||||
Core::System::GetInstance().GetCoreTiming().ScheduleEvent(cycles, et_SetTokenFinishOnMainThread,
|
Core::System::GetInstance().GetCoreTiming().ScheduleEvent(cycles, m_event_type_set_token_finish,
|
||||||
0, from);
|
0, from);
|
||||||
}
|
}
|
||||||
|
|
||||||
// SetToken
|
// SetToken
|
||||||
// THIS IS EXECUTED FROM VIDEO THREAD
|
// THIS IS EXECUTED FROM VIDEO THREAD
|
||||||
void SetToken(const u16 token, const bool interrupt, int cycles_into_future)
|
void PixelEngineManager::SetToken(const u16 token, const bool interrupt, int cycles_into_future)
|
||||||
{
|
{
|
||||||
DEBUG_LOG_FMT(PIXELENGINE, "VIDEO Backend raises INT_CAUSE_PE_TOKEN (btw, token: {:04x})", token);
|
DEBUG_LOG_FMT(PIXELENGINE, "VIDEO Backend raises INT_CAUSE_PE_TOKEN (btw, token: {:04x})", token);
|
||||||
|
|
||||||
std::lock_guard<std::mutex> lk(s_token_finish_mutex);
|
std::lock_guard<std::mutex> lk(m_token_finish_mutex);
|
||||||
|
|
||||||
s_token_pending = token;
|
m_token_pending = token;
|
||||||
s_token_interrupt_pending |= interrupt;
|
m_token_interrupt_pending |= interrupt;
|
||||||
|
|
||||||
RaiseEvent(cycles_into_future);
|
RaiseEvent(cycles_into_future);
|
||||||
}
|
}
|
||||||
|
|
||||||
// SetFinish
|
// SetFinish
|
||||||
// THIS IS EXECUTED FROM VIDEO THREAD (BPStructs.cpp) when a new frame has been drawn
|
// THIS IS EXECUTED FROM VIDEO THREAD (BPStructs.cpp) when a new frame has been drawn
|
||||||
void SetFinish(int cycles_into_future)
|
void PixelEngineManager::SetFinish(int cycles_into_future)
|
||||||
{
|
{
|
||||||
DEBUG_LOG_FMT(PIXELENGINE, "VIDEO Set Finish");
|
DEBUG_LOG_FMT(PIXELENGINE, "VIDEO Set Finish");
|
||||||
|
|
||||||
std::lock_guard<std::mutex> lk(s_token_finish_mutex);
|
std::lock_guard<std::mutex> lk(m_token_finish_mutex);
|
||||||
|
|
||||||
s_finish_interrupt_pending |= true;
|
m_finish_interrupt_pending |= true;
|
||||||
|
|
||||||
RaiseEvent(cycles_into_future);
|
RaiseEvent(cycles_into_future);
|
||||||
}
|
}
|
||||||
|
|
||||||
AlphaReadMode GetAlphaReadMode()
|
|
||||||
{
|
|
||||||
return m_AlphaRead.read_mode;
|
|
||||||
}
|
|
||||||
|
|
||||||
} // namespace PixelEngine
|
} // namespace PixelEngine
|
||||||
|
|
|
@ -3,10 +3,21 @@
|
||||||
|
|
||||||
#pragma once
|
#pragma once
|
||||||
|
|
||||||
|
#include <mutex>
|
||||||
|
|
||||||
|
#include "Common/BitField.h"
|
||||||
#include "Common/CommonTypes.h"
|
#include "Common/CommonTypes.h"
|
||||||
|
|
||||||
class PointerWrap;
|
class PointerWrap;
|
||||||
|
|
||||||
|
namespace Core
|
||||||
|
{
|
||||||
|
class System;
|
||||||
|
}
|
||||||
|
namespace CoreTiming
|
||||||
|
{
|
||||||
|
struct EventType;
|
||||||
|
}
|
||||||
namespace MMIO
|
namespace MMIO
|
||||||
{
|
{
|
||||||
class Mapping;
|
class Mapping;
|
||||||
|
@ -54,14 +65,157 @@ enum class AlphaReadMode : u16
|
||||||
ReadNone = 2, // Always read the real alpha value
|
ReadNone = 2, // Always read the real alpha value
|
||||||
};
|
};
|
||||||
|
|
||||||
void Init();
|
// Note: These enums are (assumed to be) identical to the one in BPMemory, but the base type is set
|
||||||
void DoState(PointerWrap& p);
|
// to u16 instead of u32 for BitField
|
||||||
|
enum class CompareMode : u16
|
||||||
|
{
|
||||||
|
Never = 0,
|
||||||
|
Less = 1,
|
||||||
|
Equal = 2,
|
||||||
|
LEqual = 3,
|
||||||
|
Greater = 4,
|
||||||
|
NEqual = 5,
|
||||||
|
GEqual = 6,
|
||||||
|
Always = 7
|
||||||
|
};
|
||||||
|
|
||||||
void RegisterMMIO(MMIO::Mapping* mmio, u32 base);
|
union UPEZConfReg
|
||||||
|
{
|
||||||
|
u16 hex = 0;
|
||||||
|
BitField<0, 1, bool, u16> z_comparator_enable;
|
||||||
|
BitField<1, 3, CompareMode, u16> function;
|
||||||
|
BitField<4, 1, bool, u16> z_update_enable;
|
||||||
|
};
|
||||||
|
|
||||||
// gfx backend support
|
enum class SrcBlendFactor : u16
|
||||||
void SetToken(const u16 token, const bool interrupt, int cycle_delay);
|
{
|
||||||
void SetFinish(int cycle_delay);
|
Zero = 0,
|
||||||
AlphaReadMode GetAlphaReadMode();
|
One = 1,
|
||||||
|
DstClr = 2,
|
||||||
|
InvDstClr = 3,
|
||||||
|
SrcAlpha = 4,
|
||||||
|
InvSrcAlpha = 5,
|
||||||
|
DstAlpha = 6,
|
||||||
|
InvDstAlpha = 7
|
||||||
|
};
|
||||||
|
|
||||||
|
enum class DstBlendFactor : u16
|
||||||
|
{
|
||||||
|
Zero = 0,
|
||||||
|
One = 1,
|
||||||
|
SrcClr = 2,
|
||||||
|
InvSrcClr = 3,
|
||||||
|
SrcAlpha = 4,
|
||||||
|
InvSrcAlpha = 5,
|
||||||
|
DstAlpha = 6,
|
||||||
|
InvDstAlpha = 7
|
||||||
|
};
|
||||||
|
|
||||||
|
enum class LogicOp : u16
|
||||||
|
{
|
||||||
|
Clear = 0,
|
||||||
|
And = 1,
|
||||||
|
AndReverse = 2,
|
||||||
|
Copy = 3,
|
||||||
|
AndInverted = 4,
|
||||||
|
NoOp = 5,
|
||||||
|
Xor = 6,
|
||||||
|
Or = 7,
|
||||||
|
Nor = 8,
|
||||||
|
Equiv = 9,
|
||||||
|
Invert = 10,
|
||||||
|
OrReverse = 11,
|
||||||
|
CopyInverted = 12,
|
||||||
|
OrInverted = 13,
|
||||||
|
Nand = 14,
|
||||||
|
Set = 15
|
||||||
|
};
|
||||||
|
|
||||||
|
union UPEAlphaConfReg
|
||||||
|
{
|
||||||
|
u16 hex = 0;
|
||||||
|
BitField<0, 1, bool, u16> blend; // Set for GX_BM_BLEND or GX_BM_SUBTRACT
|
||||||
|
BitField<1, 1, bool, u16> logic; // Set for GX_BM_LOGIC
|
||||||
|
BitField<2, 1, bool, u16> dither;
|
||||||
|
BitField<3, 1, bool, u16> color_update_enable;
|
||||||
|
BitField<4, 1, bool, u16> alpha_update_enable;
|
||||||
|
BitField<5, 3, DstBlendFactor, u16> dst_factor;
|
||||||
|
BitField<8, 3, SrcBlendFactor, u16> src_factor;
|
||||||
|
BitField<11, 1, bool, u16> subtract; // Set for GX_BM_SUBTRACT
|
||||||
|
BitField<12, 4, LogicOp, u16> logic_op;
|
||||||
|
};
|
||||||
|
|
||||||
|
union UPEDstAlphaConfReg
|
||||||
|
{
|
||||||
|
u16 hex = 0;
|
||||||
|
BitField<0, 8, u8, u16> alpha;
|
||||||
|
BitField<8, 1, bool, u16> enable;
|
||||||
|
};
|
||||||
|
|
||||||
|
union UPEAlphaModeConfReg
|
||||||
|
{
|
||||||
|
u16 hex = 0;
|
||||||
|
BitField<0, 8, u8, u16> threshold;
|
||||||
|
// Yagcd and libogc use 8 bits for this, but the enum only needs 3
|
||||||
|
BitField<8, 3, CompareMode, u16> compare_mode;
|
||||||
|
};
|
||||||
|
|
||||||
|
union UPEAlphaReadReg
|
||||||
|
{
|
||||||
|
u16 hex = 0;
|
||||||
|
BitField<0, 2, AlphaReadMode, u16> read_mode;
|
||||||
|
};
|
||||||
|
|
||||||
|
// fifo Control Register
|
||||||
|
union UPECtrlReg
|
||||||
|
{
|
||||||
|
u16 hex = 0;
|
||||||
|
BitField<0, 1, bool, u16> pe_token_enable;
|
||||||
|
BitField<1, 1, bool, u16> pe_finish_enable;
|
||||||
|
BitField<2, 1, bool, u16> pe_token; // Write only
|
||||||
|
BitField<3, 1, bool, u16> pe_finish; // Write only
|
||||||
|
};
|
||||||
|
|
||||||
|
class PixelEngineManager
|
||||||
|
{
|
||||||
|
public:
|
||||||
|
void Init();
|
||||||
|
void DoState(PointerWrap& p);
|
||||||
|
|
||||||
|
void RegisterMMIO(MMIO::Mapping* mmio, u32 base);
|
||||||
|
|
||||||
|
// gfx backend support
|
||||||
|
void SetToken(const u16 token, const bool interrupt, int cycle_delay);
|
||||||
|
void SetFinish(int cycle_delay);
|
||||||
|
AlphaReadMode GetAlphaReadMode() const { return m_alpha_read.read_mode; }
|
||||||
|
|
||||||
|
private:
|
||||||
|
void RaiseEvent(int cycles_into_future);
|
||||||
|
void UpdateInterrupts();
|
||||||
|
void SetTokenFinish_OnMainThread(Core::System& system, u64 userdata, s64 cycles_late);
|
||||||
|
|
||||||
|
static void SetTokenFinish_OnMainThread_Static(Core::System& system, u64 userdata,
|
||||||
|
s64 cycles_late);
|
||||||
|
|
||||||
|
// STATE_TO_SAVE
|
||||||
|
UPEZConfReg m_z_conf;
|
||||||
|
UPEAlphaConfReg m_alpha_conf;
|
||||||
|
UPEDstAlphaConfReg m_dst_alpha_conf;
|
||||||
|
UPEAlphaModeConfReg m_alpha_mode_conf;
|
||||||
|
UPEAlphaReadReg m_alpha_read;
|
||||||
|
UPECtrlReg m_control;
|
||||||
|
|
||||||
|
std::mutex m_token_finish_mutex;
|
||||||
|
u16 m_token = 0;
|
||||||
|
u16 m_token_pending = 0;
|
||||||
|
bool m_token_interrupt_pending = false;
|
||||||
|
bool m_finish_interrupt_pending = false;
|
||||||
|
bool m_event_raised = false;
|
||||||
|
|
||||||
|
bool m_signal_token_interrupt = false;
|
||||||
|
bool m_signal_finish_interrupt = false;
|
||||||
|
|
||||||
|
CoreTiming::EventType* m_event_type_set_token_finish = nullptr;
|
||||||
|
};
|
||||||
|
|
||||||
} // namespace PixelEngine
|
} // namespace PixelEngine
|
||||||
|
|
|
@ -278,7 +278,8 @@ u32 Renderer::AccessEFB(EFBAccessType type, u32 x, u32 y, u32 poke_data)
|
||||||
}
|
}
|
||||||
|
|
||||||
// check what to do with the alpha channel (GX_PokeAlphaRead)
|
// check what to do with the alpha channel (GX_PokeAlphaRead)
|
||||||
PixelEngine::AlphaReadMode alpha_read_mode = PixelEngine::GetAlphaReadMode();
|
PixelEngine::AlphaReadMode alpha_read_mode =
|
||||||
|
Core::System::GetInstance().GetPixelEngine().GetAlphaReadMode();
|
||||||
|
|
||||||
if (alpha_read_mode == PixelEngine::AlphaReadMode::ReadNone)
|
if (alpha_read_mode == PixelEngine::AlphaReadMode::ReadNone)
|
||||||
{
|
{
|
||||||
|
|
|
@ -325,7 +325,7 @@ void VideoBackendBase::InitializeShared()
|
||||||
auto& command_processor = system.GetCommandProcessor();
|
auto& command_processor = system.GetCommandProcessor();
|
||||||
command_processor.Init(system);
|
command_processor.Init(system);
|
||||||
system.GetFifo().Init(system);
|
system.GetFifo().Init(system);
|
||||||
PixelEngine::Init();
|
system.GetPixelEngine().Init();
|
||||||
BPInit();
|
BPInit();
|
||||||
VertexLoaderManager::Init();
|
VertexLoaderManager::Init();
|
||||||
VertexShaderManager::Init();
|
VertexShaderManager::Init();
|
||||||
|
|
|
@ -68,7 +68,7 @@ void VideoCommon_DoState(PointerWrap& p)
|
||||||
command_processor.DoState(p);
|
command_processor.DoState(p);
|
||||||
p.DoMarker("CommandProcessor");
|
p.DoMarker("CommandProcessor");
|
||||||
|
|
||||||
PixelEngine::DoState(p);
|
system.GetPixelEngine().DoState(p);
|
||||||
p.DoMarker("PixelEngine");
|
p.DoMarker("PixelEngine");
|
||||||
|
|
||||||
// the old way of replaying current bpmem as writes to push side effects to pixel shader manager
|
// the old way of replaying current bpmem as writes to push side effects to pixel shader manager
|
||||||
|
|
Loading…
Reference in New Issue