XEmitter: overload MOVBE()
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20ded4c1e5
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eb13aa43fe
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@ -870,38 +870,25 @@ void XEmitter::MOVZX(int dbits, int sbits, X64Reg dest, OpArg src)
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src.WriteRest(this);
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}
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void XEmitter::MOVBE(int bits, const OpArg& dest, const OpArg& src)
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void XEmitter::WriteMOVBE(int bits, u8 op, X64Reg reg, OpArg arg)
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{
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_assert_msg_(DYNA_REC, cpu_info.bMOVBE, "Generating MOVBE on a system that does not support it.");
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if (bits == 8)
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{
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MOV(bits, dest, src);
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MOV(8, op & 1 ? arg : R(reg), op & 1 ? R(reg) : arg);
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return;
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}
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if (bits == 16)
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Write8(0x66);
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if (dest.IsSimpleReg())
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{
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_assert_msg_(DYNA_REC, !src.IsSimpleReg() && !src.IsImm(), "MOVBE: Loading from !mem");
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src.WriteRex(this, bits, bits, dest.GetSimpleReg());
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Write8(0x0F); Write8(0x38); Write8(0xF0);
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src.WriteRest(this, 0, dest.GetSimpleReg());
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}
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else if (src.IsSimpleReg())
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{
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_assert_msg_(DYNA_REC, !dest.IsSimpleReg() && !dest.IsImm(), "MOVBE: Storing to !mem");
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dest.WriteRex(this, bits, bits, src.GetSimpleReg());
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Write8(0x0F); Write8(0x38); Write8(0xF1);
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dest.WriteRest(this, 0, src.GetSimpleReg());
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}
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else
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{
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_assert_msg_(DYNA_REC, 0, "MOVBE: Not loading or storing to mem");
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}
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_assert_msg_(DYNA_REC, !arg.IsSimpleReg() && !arg.IsImm(), "MOVBE: need r<-m or m<-r!");
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arg.WriteRex(this, bits, bits, reg);
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Write8(0x0F);
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Write8(0x38);
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Write8(op);
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arg.WriteRest(this, 0, reg);
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}
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void XEmitter::MOVBE(int bits, X64Reg dest, const OpArg& src) {WriteMOVBE(bits, 0xF0, dest, src);}
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void XEmitter::MOVBE(int bits, const OpArg& dest, X64Reg src) {WriteMOVBE(bits, 0xF1, src, dest);}
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void XEmitter::LEA(int bits, X64Reg dest, OpArg src)
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{
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@ -299,6 +299,7 @@ private:
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void WriteVEXOp(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes = 0);
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void WriteBMI1Op(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes = 0);
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void WriteBMI2Op(int size, u8 opPrefix, u16 op, X64Reg regOp1, X64Reg regOp2, OpArg arg, int extrabytes = 0);
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void WriteMOVBE(int bits, u8 op, X64Reg regOp, OpArg arg);
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void WriteFloatLoadStore(int bits, FloatOp op, FloatOp op_80b, OpArg arg);
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void WriteNormalOp(XEmitter *emit, int bits, NormalOp op, const OpArg &a1, const OpArg &a2);
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@ -476,7 +477,8 @@ public:
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void MOVZX(int dbits, int sbits, X64Reg dest, OpArg src);
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// Available only on Atom or >= Haswell so far. Test with cpu_info.bMOVBE.
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void MOVBE(int dbits, const OpArg& dest, const OpArg& src);
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void MOVBE(int bits, X64Reg dest, const OpArg& src);
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void MOVBE(int bits, const OpArg& dest, X64Reg src);
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// Available only on AMD >= Phenom or Intel >= Haswell
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void LZCNT(int bits, X64Reg dest, OpArg src);
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@ -27,7 +27,7 @@ void EmuCodeBlock::LoadAndSwap(int size, Gen::X64Reg dst, const Gen::OpArg& src)
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{
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if (cpu_info.bMOVBE)
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{
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MOVBE(size, R(dst), src);
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MOVBE(size, dst, src);
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}
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else
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{
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@ -40,7 +40,7 @@ void EmuCodeBlock::SwapAndStore(int size, const Gen::OpArg& dst, Gen::X64Reg src
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{
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if (cpu_info.bMOVBE)
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{
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MOVBE(size, dst, R(src));
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MOVBE(size, dst, src);
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}
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else
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{
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@ -451,7 +451,7 @@ u8 *EmuCodeBlock::UnsafeWriteRegToReg(OpArg reg_value, X64Reg reg_addr, int acce
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{
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if (cpu_info.bMOVBE)
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{
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MOVBE(accessSize, dest, reg_value);
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MOVBE(accessSize, dest, reg_value.GetSimpleReg());
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}
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else
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{
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@ -609,12 +609,12 @@ TEST_F(x64EmitterTest, MOVZX)
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TEST_F(x64EmitterTest, MOVBE)
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{
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emitter->MOVBE(16, R(RAX), MatR(R12));
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emitter->MOVBE(16, MatR(RAX), R(R12));
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emitter->MOVBE(32, R(RAX), MatR(R12));
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emitter->MOVBE(32, MatR(RAX), R(R12));
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emitter->MOVBE(64, R(RAX), MatR(R12));
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emitter->MOVBE(64, MatR(RAX), R(R12));
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emitter->MOVBE(16, RAX, MatR(R12));
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emitter->MOVBE(16, MatR(RAX), R12);
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emitter->MOVBE(32, RAX, MatR(R12));
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emitter->MOVBE(32, MatR(RAX), R12);
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emitter->MOVBE(64, RAX, MatR(R12));
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emitter->MOVBE(64, MatR(RAX), R12);
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ExpectDisassembly("movbe ax, word ptr ds:[r12] "
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"movbe word ptr ds:[rax], r12w "
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"movbe eax, dword ptr ds:[r12] "
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