Further optimised the JIT cache lookup. Attempted to fix the Wii games in ICC builds.
git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@6136 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
parent
d5bae7e0ad
commit
eaa3371f92
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@ -77,7 +77,7 @@ void Jit64AsmRoutineManager::Generate()
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dispatcher = GetCodePtr();
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dispatcher = GetCodePtr();
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// The result of slice decrementation should be in flags if somebody jumped here
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// The result of slice decrementation should be in flags if somebody jumped here
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// IMPORTANT - We jump on negative, not carry!!!
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// IMPORTANT - We jump on negative, not carry!!!
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FixupBranch bail = J_CC(CC_BE);
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FixupBranch bail = J_CC(CC_BE, true);
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if (Core::g_CoreStartupParameter.bEnableDebugging)
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if (Core::g_CoreStartupParameter.bEnableDebugging)
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{
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{
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@ -95,8 +95,72 @@ void Jit64AsmRoutineManager::Generate()
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MOV(32, R(EAX), M(&PowerPC::ppcState.pc));
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MOV(32, R(EAX), M(&PowerPC::ppcState.pc));
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dispatcherPcInEAX = GetCodePtr();
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dispatcherPcInEAX = GetCodePtr();
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FixupBranch needinst = J(true);
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#ifdef JIT_UNLIMITED_ICACHE
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const u8* haveinst = GetCodePtr();
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u32 mask = 0;
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FixupBranch no_mem;
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FixupBranch exit_mem;
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FixupBranch exit_vmem;
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if (Core::g_CoreStartupParameter.bWii)
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mask = JIT_ICACHE_EXRAM_BIT;
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if (Core::g_CoreStartupParameter.bMMU || Core::g_CoreStartupParameter.iTLBHack)
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mask |= JIT_ICACHE_VMEM_BIT;
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if (Core::g_CoreStartupParameter.bWii || Core::g_CoreStartupParameter.bMMU || Core::g_CoreStartupParameter.iTLBHack)
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{
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TEST(32, R(EAX), Imm32(mask));
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no_mem = J_CC(CC_NZ);
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}
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AND(32, R(EAX), Imm32(JIT_ICACHE_MASK));
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#ifdef _M_IX86
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MOV(32, R(EAX), MDisp(EAX, (u32)jit->GetBlockCache()->GetICache()));
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#else
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MOV(64, R(RSI), Imm64((u64)jit->GetBlockCache()->GetICache()));
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MOV(32, R(EAX), MComplex(RSI, EAX, SCALE_1, 0));
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#endif
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if (Core::g_CoreStartupParameter.bWii || Core::g_CoreStartupParameter.bMMU || Core::g_CoreStartupParameter.iTLBHack)
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{
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exit_mem = J();
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SetJumpTarget(no_mem);
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}
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if (Core::g_CoreStartupParameter.bMMU || Core::g_CoreStartupParameter.iTLBHack)
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{
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TEST(32, R(EAX), Imm32(JIT_ICACHE_VMEM_BIT));
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FixupBranch no_vmem = J_CC(CC_Z);
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AND(32, R(EAX), Imm32(JIT_ICACHE_MASK));
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#ifdef _M_IX86
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MOV(32, R(EAX), MDisp(EAX, (u32)jit->GetBlockCache()->GetICacheVMEM()));
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#else
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MOV(64, R(RSI), Imm64((u64)jit->GetBlockCache()->GetICacheVMEM()));
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MOV(32, R(EAX), MComplex(RSI, EAX, SCALE_1, 0));
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#endif
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if (Core::g_CoreStartupParameter.bWii) exit_vmem = J();
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SetJumpTarget(no_vmem);
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}
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if (Core::g_CoreStartupParameter.bWii)
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{
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TEST(32, R(EAX), Imm32(JIT_ICACHE_EXRAM_BIT));
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FixupBranch no_exram = J_CC(CC_Z);
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AND(32, R(EAX), Imm32(JIT_ICACHEEX_MASK));
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#ifdef _M_IX86
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MOV(32, R(EAX), MDisp(EAX, (u32)jit->GetBlockCache()->GetICacheEx()));
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#else
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MOV(64, R(RSI), Imm64((u64)jit->GetBlockCache()->GetICacheEx()));
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MOV(32, R(EAX), MComplex(RSI, EAX, SCALE_1, 0));
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#endif
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SetJumpTarget(no_exram);
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}
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if (Core::g_CoreStartupParameter.bWii || Core::g_CoreStartupParameter.bMMU || Core::g_CoreStartupParameter.iTLBHack)
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SetJumpTarget(exit_mem);
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if (Core::g_CoreStartupParameter.bWii && (Core::g_CoreStartupParameter.bMMU || Core::g_CoreStartupParameter.iTLBHack))
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SetJumpTarget(exit_vmem);
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#else
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#ifdef _M_IX86
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AND(32, R(EAX), Imm32(Memory::MEMVIEW32_MASK));
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MOV(32, R(EBX), Imm32((u32)Memory::base));
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MOV(32, R(EAX), MComplex(EBX, EAX, SCALE_1, 0));
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#else
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MOV(32, R(EAX), MComplex(RBX, RAX, SCALE_1, 0));
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#endif
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#endif
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TEST(32, R(EAX), Imm32(0xFC));
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TEST(32, R(EAX), Imm32(0xFC));
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FixupBranch notfound = J_CC(CC_NZ);
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FixupBranch notfound = J_CC(CC_NZ);
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@ -133,7 +197,7 @@ void Jit64AsmRoutineManager::Generate()
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ABI_CallFunction(reinterpret_cast<void *>(&PowerPC::CheckExceptions));
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ABI_CallFunction(reinterpret_cast<void *>(&PowerPC::CheckExceptions));
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MOV(32, R(EAX), M(&NPC));
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MOV(32, R(EAX), M(&NPC));
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MOV(32, M(&PC), R(EAX));
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MOV(32, M(&PC), R(EAX));
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JMP(dispatcher);
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JMP(dispatcher, true);
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SetJumpTarget(bail);
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SetJumpTarget(bail);
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doTiming = GetCodePtr();
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doTiming = GetCodePtr();
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@ -157,77 +221,6 @@ void Jit64AsmRoutineManager::Generate()
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ABI_PopAllCalleeSavedRegsAndAdjustStack();
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ABI_PopAllCalleeSavedRegsAndAdjustStack();
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RET();
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RET();
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SetJumpTarget(needinst);
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#ifdef JIT_UNLIMITED_ICACHE
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u32 mask = 0;
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FixupBranch no_mem;
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FixupBranch exit_mem;
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FixupBranch exit_vmem;
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if (Core::g_CoreStartupParameter.bWii)
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mask = JIT_ICACHE_EXRAM_BIT;
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if (Core::g_CoreStartupParameter.bMMU || Core::g_CoreStartupParameter.iTLBHack)
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mask |= JIT_ICACHE_VMEM_BIT;
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if (Core::g_CoreStartupParameter.bWii || Core::g_CoreStartupParameter.bMMU || Core::g_CoreStartupParameter.iTLBHack)
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{
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TEST(32, R(EAX), Imm32(mask));
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no_mem = J_CC(CC_NZ);
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}
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AND(32, R(EAX), Imm32(JIT_ICACHE_MASK));
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#ifdef _M_IX86
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MOV(32, R(EAX), MDisp(EAX, (u32)jit->GetBlockCache()->GetICache()));
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#else
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MOV(64, R(RSI), Imm64((u64)jit->GetBlockCache()->GetICache()));
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MOV(32, R(EAX), MComplex(RSI, EAX, SCALE_1, 0));
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#endif
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if (Core::g_CoreStartupParameter.bWii || Core::g_CoreStartupParameter.bMMU || Core::g_CoreStartupParameter.iTLBHack)
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{
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exit_mem = J();
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SetJumpTarget(no_mem);
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}
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if (Core::g_CoreStartupParameter.bMMU || Core::g_CoreStartupParameter.iTLBHack)
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{
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TEST(32, R(EAX), Imm32(JIT_ICACHE_VMEM_BIT));
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FixupBranch no_vmem = J_CC(CC_Z);
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AND(32, R(EAX), Imm32(JIT_ICACHE_MASK));
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#ifdef _M_IX86
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MOV(32, R(EAX), MDisp(EAX, (u32)jit->GetBlockCache()->GetICacheVMEM()));
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#else
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MOV(64, R(RSI), Imm64((u64)jit->GetBlockCache()->GetICacheVMEM()));
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MOV(32, R(EAX), MComplex(RSI, EAX, SCALE_1, 0));
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#endif
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if (Core::g_CoreStartupParameter.bWii) exit_vmem = J();
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SetJumpTarget(no_vmem);
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}
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if (Core::g_CoreStartupParameter.bWii)
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{
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TEST(32, R(EAX), Imm32(JIT_ICACHE_EXRAM_BIT));
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FixupBranch no_exram = J_CC(CC_Z);
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AND(32, R(EAX), Imm32(JIT_ICACHEEX_MASK));
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#ifdef _M_IX86
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MOV(32, R(EAX), MDisp(EAX, (u32)jit->GetBlockCache()->GetICacheEx()));
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#else
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MOV(64, R(RSI), Imm64((u64)jit->GetBlockCache()->GetICacheEx()));
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MOV(32, R(EAX), MComplex(RSI, EAX, SCALE_1, 0));
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#endif
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SetJumpTarget(no_exram);
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}
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if (Core::g_CoreStartupParameter.bWii || Core::g_CoreStartupParameter.bMMU || Core::g_CoreStartupParameter.iTLBHack)
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SetJumpTarget(exit_mem);
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if (Core::g_CoreStartupParameter.bWii)
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SetJumpTarget(exit_vmem);
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#else
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#ifdef _M_IX86
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AND(32, R(EAX), Imm32(Memory::MEMVIEW32_MASK));
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MOV(32, R(EBX), Imm32((u32)Memory::base));
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MOV(32, R(EAX), MComplex(EBX, EAX, SCALE_1, 0));
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#else
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MOV(32, R(EAX), MComplex(RBX, RAX, SCALE_1, 0));
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#endif
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#endif
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JMP(haveinst, true);
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breakpointBailout = GetCodePtr();
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breakpointBailout = GetCodePtr();
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//Landing pad for drec space
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//Landing pad for drec space
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ABI_PopAllCalleeSavedRegsAndAdjustStack();
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ABI_PopAllCalleeSavedRegsAndAdjustStack();
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@ -79,7 +79,7 @@ void JitILAsmRoutineManager::Generate()
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//This is the place for CPUCompare!
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//This is the place for CPUCompare!
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//The result of slice decrement should be in flags if somebody jumped here
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//The result of slice decrement should be in flags if somebody jumped here
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FixupBranch bail = J_CC(CC_BE);
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FixupBranch bail = J_CC(CC_BE, true);
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if (Core::g_CoreStartupParameter.bEnableDebugging)
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if (Core::g_CoreStartupParameter.bEnableDebugging)
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{
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{
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@ -97,75 +97,6 @@ void JitILAsmRoutineManager::Generate()
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MOV(32, R(EAX), M(&PowerPC::ppcState.pc));
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MOV(32, R(EAX), M(&PowerPC::ppcState.pc));
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dispatcherPcInEAX = GetCodePtr();
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dispatcherPcInEAX = GetCodePtr();
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FixupBranch needinst = J(true);
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const u8* haveinst = GetCodePtr();
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TEST(32, R(EAX), Imm32(0xFC));
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FixupBranch notfound = J_CC(CC_NZ);
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BSWAP(32, EAX);
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//IDEA - we have 26 bits, why not just use offsets from base of code?
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if (enableDebug)
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{
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ADD(32, M(&PowerPC::ppcState.DebugCount), Imm8(1));
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}
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//grab from list and jump to it
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#ifdef _M_IX86
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MOV(32, R(EDX), ImmPtr(jit->GetBlockCache()->GetCodePointers()));
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JMPptr(MComplex(EDX, EAX, 4, 0));
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#else
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JMPptr(MComplex(R15, RAX, 8, 0));
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#endif
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SetJumpTarget(notfound);
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//Ok, no block, let's jit
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#ifdef _M_IX86
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ABI_AlignStack(4);
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PUSH(32, M(&PowerPC::ppcState.pc));
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CALL(reinterpret_cast<void *>(&Jit));
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ABI_RestoreStack(4);
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#else
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MOV(32, R(ABI_PARAM1), M(&PowerPC::ppcState.pc));
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CALL((void *)&Jit);
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#endif
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JMP(dispatcherNoCheck); // no point in special casing this
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//FP blocks test for FPU available, jump here if false
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fpException = AlignCode4();
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MOV(32, R(EAX), M(&PC));
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MOV(32, M(&NPC), R(EAX));
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OR(32, M(&PowerPC::ppcState.Exceptions), Imm32(EXCEPTION_FPU_UNAVAILABLE));
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ABI_CallFunction(reinterpret_cast<void *>(&PowerPC::CheckExceptions));
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MOV(32, R(EAX), M(&NPC));
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MOV(32, M(&PC), R(EAX));
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JMP(dispatcher);
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SetJumpTarget(bail);
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doTiming = GetCodePtr();
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ABI_CallFunction(reinterpret_cast<void *>(&CoreTiming::Advance));
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testExceptions = GetCodePtr();
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TEST(32, M(&PowerPC::ppcState.Exceptions), Imm32(0xFFFFFFFF));
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FixupBranch skipExceptions = J_CC(CC_Z);
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MOV(32, R(EAX), M(&PC));
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MOV(32, M(&NPC), R(EAX));
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ABI_CallFunction(reinterpret_cast<void *>(&PowerPC::CheckExceptions));
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MOV(32, R(EAX), M(&NPC));
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MOV(32, M(&PC), R(EAX));
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SetJumpTarget(skipExceptions);
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TEST(32, M((void*)PowerPC::GetStatePtr()), Imm32(0xFFFFFFFF));
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J_CC(CC_Z, outerLoop, true);
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//Landing pad for drec space
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ABI_PopAllCalleeSavedRegsAndAdjustStack();
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RET();
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breakpointBailout = GetCodePtr();
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//Landing pad for drec space
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ABI_PopAllCalleeSavedRegsAndAdjustStack();
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RET();
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SetJumpTarget(needinst);
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#ifdef JIT_UNLIMITED_ICACHE
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#ifdef JIT_UNLIMITED_ICACHE
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u32 mask = 0;
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u32 mask = 0;
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FixupBranch no_mem;
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FixupBranch no_mem;
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@ -221,7 +152,7 @@ void JitILAsmRoutineManager::Generate()
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}
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}
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if (Core::g_CoreStartupParameter.bWii || Core::g_CoreStartupParameter.bMMU || Core::g_CoreStartupParameter.iTLBHack)
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if (Core::g_CoreStartupParameter.bWii || Core::g_CoreStartupParameter.bMMU || Core::g_CoreStartupParameter.iTLBHack)
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SetJumpTarget(exit_mem);
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SetJumpTarget(exit_mem);
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if (Core::g_CoreStartupParameter.bWii)
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if (Core::g_CoreStartupParameter.bWii && (Core::g_CoreStartupParameter.bMMU || Core::g_CoreStartupParameter.iTLBHack))
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SetJumpTarget(exit_vmem);
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SetJumpTarget(exit_vmem);
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#else
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#else
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#ifdef _M_IX86
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#ifdef _M_IX86
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MOV(32, R(EAX), MComplex(RBX, RAX, SCALE_1, 0));
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MOV(32, R(EAX), MComplex(RBX, RAX, SCALE_1, 0));
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#endif
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#endif
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#endif
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#endif
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JMP(haveinst, true);
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TEST(32, R(EAX), Imm32(0xFC));
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FixupBranch notfound = J_CC(CC_NZ);
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BSWAP(32, EAX);
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//IDEA - we have 26 bits, why not just use offsets from base of code?
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if (enableDebug)
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{
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ADD(32, M(&PowerPC::ppcState.DebugCount), Imm8(1));
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}
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//grab from list and jump to it
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#ifdef _M_IX86
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MOV(32, R(EDX), ImmPtr(jit->GetBlockCache()->GetCodePointers()));
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JMPptr(MComplex(EDX, EAX, 4, 0));
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#else
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JMPptr(MComplex(R15, RAX, 8, 0));
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#endif
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SetJumpTarget(notfound);
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//Ok, no block, let's jit
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#ifdef _M_IX86
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ABI_AlignStack(4);
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PUSH(32, M(&PowerPC::ppcState.pc));
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CALL(reinterpret_cast<void *>(&Jit));
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ABI_RestoreStack(4);
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#else
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MOV(32, R(ABI_PARAM1), M(&PowerPC::ppcState.pc));
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CALL((void *)&Jit);
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#endif
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JMP(dispatcherNoCheck); // no point in special casing this
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//FP blocks test for FPU available, jump here if false
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fpException = AlignCode4();
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MOV(32, R(EAX), M(&PC));
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MOV(32, M(&NPC), R(EAX));
|
||||||
|
OR(32, M(&PowerPC::ppcState.Exceptions), Imm32(EXCEPTION_FPU_UNAVAILABLE));
|
||||||
|
ABI_CallFunction(reinterpret_cast<void *>(&PowerPC::CheckExceptions));
|
||||||
|
MOV(32, R(EAX), M(&NPC));
|
||||||
|
MOV(32, M(&PC), R(EAX));
|
||||||
|
JMP(dispatcher, true);
|
||||||
|
|
||||||
|
SetJumpTarget(bail);
|
||||||
|
doTiming = GetCodePtr();
|
||||||
|
|
||||||
|
ABI_CallFunction(reinterpret_cast<void *>(&CoreTiming::Advance));
|
||||||
|
|
||||||
|
testExceptions = GetCodePtr();
|
||||||
|
TEST(32, M(&PowerPC::ppcState.Exceptions), Imm32(0xFFFFFFFF));
|
||||||
|
FixupBranch skipExceptions = J_CC(CC_Z);
|
||||||
|
MOV(32, R(EAX), M(&PC));
|
||||||
|
MOV(32, M(&NPC), R(EAX));
|
||||||
|
ABI_CallFunction(reinterpret_cast<void *>(&PowerPC::CheckExceptions));
|
||||||
|
MOV(32, R(EAX), M(&NPC));
|
||||||
|
MOV(32, M(&PC), R(EAX));
|
||||||
|
SetJumpTarget(skipExceptions);
|
||||||
|
|
||||||
|
TEST(32, M((void*)PowerPC::GetStatePtr()), Imm32(0xFFFFFFFF));
|
||||||
|
J_CC(CC_Z, outerLoop, true);
|
||||||
|
//Landing pad for drec space
|
||||||
|
ABI_PopAllCalleeSavedRegsAndAdjustStack();
|
||||||
|
RET();
|
||||||
|
|
||||||
|
breakpointBailout = GetCodePtr();
|
||||||
|
//Landing pad for drec space
|
||||||
|
ABI_PopAllCalleeSavedRegsAndAdjustStack();
|
||||||
|
RET();
|
||||||
|
|
||||||
GenerateCommon();
|
GenerateCommon();
|
||||||
}
|
}
|
||||||
|
|
Loading…
Reference in New Issue