MMU: fix rollback in DSIs on page-crossing stores
I don't know if this affected anything, but it was subtly wrong. Also reorganize the loads to match, for consistency.
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acb583e607
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@ -130,43 +130,35 @@ __forceinline void ReadFromHardware(U &_var, const u32 em_address, Memory::XChec
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// Handle loads that cross page boundaries (ewwww)
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if (sizeof(T) > 1 && (em_address & (HW_PAGE_SIZE - 1)) > HW_PAGE_SIZE - sizeof(T))
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{
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_var = 0;
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// This could be unaligned down to the byte level... hopefully this is rare, so doing it this
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// way isn't too terrible.
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// TODO: floats on non-word-aligned boundaries should technically cause alignment exceptions.
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// Note that "word" means 32-bit, so paired singles or doubles might still be 32-bit aligned!
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u32 tlb_addr = TranslateAddress(em_address, flag);
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u32 em_address_next_page = (em_address + sizeof(T) - 1) & ~(HW_PAGE_SIZE - 1);
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u32 tlb_addr_next_page = TranslateAddress(em_address_next_page, flag);
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if (tlb_addr == 0 || tlb_addr_next_page == 0)
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{
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if (flag == FLAG_READ)
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{
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u32 exception_addr = tlb_addr == 0 ? em_address : em_address_next_page;
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if (!SConfig::GetInstance().m_LocalCoreStartupParameter.bMMU)
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PanicAlertT("Invalid Read at 0x%08x, PC = 0x%08x ", exception_addr, PC);
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else
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GenerateDSIException(exception_addr, false);
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}
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return;
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}
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_var = 0;
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for (u32 addr = em_address; addr < em_address + sizeof(T); addr++, tlb_addr++)
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{
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// Start of the new page... translate the address again!
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if (!(addr & (HW_PAGE_SIZE-1)))
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tlb_addr = TranslateAddress(addr, flag);
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// Important: we need to generate the DSI on the first store that caused the fault, NOT
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// the address of the start of the load.
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if (tlb_addr == 0)
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{
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if (flag == FLAG_READ)
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{
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if (!SConfig::GetInstance().m_LocalCoreStartupParameter.bMMU)
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PanicAlertT("Invalid Read at 0x%08x, PC = 0x%08x ", em_address, PC);
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else
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GenerateDSIException(addr, false);
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break;
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}
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}
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if (addr == em_address_next_page)
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tlb_addr = tlb_addr_next_page;
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_var <<= 8;
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if (m_pEXRAM && (tlb_addr & 0xF0000000) == 0x10000000)
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_var |= m_pEXRAM[tlb_addr & EXRAM_MASK];
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else
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{
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if (m_pEXRAM && (tlb_addr & 0xF0000000) == 0x10000000)
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{
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_var <<= 8;
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_var |= m_pEXRAM[tlb_addr & EXRAM_MASK];
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}
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else
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{
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_var <<= 8;
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_var |= m_pRAM[tlb_addr & RAM_MASK];
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}
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}
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_var |= m_pRAM[tlb_addr & RAM_MASK];
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}
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}
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else
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@ -271,35 +263,30 @@ __forceinline void WriteToHardware(u32 em_address, const T data, Memory::XCheckT
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if (sizeof(T) > 1 && (em_address & (HW_PAGE_SIZE-1)) > HW_PAGE_SIZE - sizeof(T))
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{
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T val = bswap(data);
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// We need to check both addresses before writing in case there's a DSI.
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u32 tlb_addr = TranslateAddress(em_address, flag);
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for (u32 addr = em_address; addr < em_address + sizeof(T); addr++, tlb_addr++)
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u32 em_address_next_page = (em_address + sizeof(T) - 1) & ~(HW_PAGE_SIZE - 1);
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u32 tlb_addr_next_page = TranslateAddress(em_address_next_page, flag);
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if (tlb_addr == 0 || tlb_addr_next_page == 0)
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{
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if (!(addr & (HW_PAGE_SIZE-1)))
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tlb_addr = TranslateAddress(addr, flag);
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if (tlb_addr == 0)
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if (flag == FLAG_WRITE)
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{
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if (flag == FLAG_WRITE)
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{
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if (!SConfig::GetInstance().m_LocalCoreStartupParameter.bMMU)
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PanicAlertT("Invalid Write to 0x%08x, PC = 0x%08x ", em_address, PC);
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else
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GenerateDSIException(addr, true);
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break;
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}
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}
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else
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{
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if (m_pEXRAM && (tlb_addr & 0xF0000000) == 0x10000000)
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{
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m_pEXRAM[tlb_addr & EXRAM_MASK] = (u8)val;
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val >>= 8;
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}
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u32 exception_addr = tlb_addr == 0 ? em_address : em_address_next_page;
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if (!SConfig::GetInstance().m_LocalCoreStartupParameter.bMMU)
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PanicAlertT("Invalid Write to 0x%08x, PC = 0x%08x ", exception_addr, PC);
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else
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{
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m_pRAM[tlb_addr & RAM_MASK] = (u8)val;
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val >>= 8;
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}
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GenerateDSIException(exception_addr, true);
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}
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return;
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}
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for (u32 addr = em_address; addr < em_address + sizeof(T); addr++, tlb_addr++, val >>= 8)
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{
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if (addr == em_address_next_page)
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tlb_addr = tlb_addr_next_page;
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if (m_pEXRAM && (tlb_addr & 0xF0000000) == 0x10000000)
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m_pEXRAM[tlb_addr & EXRAM_MASK] = (u8)val;
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else
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m_pRAM[tlb_addr & RAM_MASK] = (u8)val;
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}
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}
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else
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