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JitIL: Fix a bug in floatpoint load/store instructions. 

The regBuildMemAddress function already clears the address register.
Not only is clearing it again pointless, regBuildMemAddress uses the
bits in IInfo slightly diffrently and the second clear can clear
the wrong registers causing bugs if something else actually needs to
use those registers.
This commit is contained in:
Scott Mansell 2015-04-05 20:17:50 +12:00
parent 38236fb8e8
commit e9459fb30a
1 changed files with 0 additions and 6 deletions
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6
Source/Core/Core/PowerPC/Jit64IL/IR_X86.cpp
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@ -1563,7 +1563,6 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, u32 exitAddress)
RI.Jit->SafeLoadToReg(RSCRATCH2, info.first, 32, info.second, regsInUse(RI), false); RI.Jit->SafeLoadToReg(RSCRATCH2, info.first, 32, info.second, regsInUse(RI), false);
Jit->MOVD_xmm(reg, R(RSCRATCH2)); Jit->MOVD_xmm(reg, R(RSCRATCH2));
RI.fregs[reg] = I; RI.fregs[reg] = I;
regNormalRegClear(RI, I);
break; break;
} }
case LoadDouble: case LoadDouble:
@ -1577,7 +1576,6 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, u32 exitAddress)
RI.Jit->SafeLoadToReg(RSCRATCH2, info.first, 64, info.second, regsInUse(RI), false); RI.Jit->SafeLoadToReg(RSCRATCH2, info.first, 64, info.second, regsInUse(RI), false);
Jit->MOVQ_xmm(reg, R(RSCRATCH2)); Jit->MOVQ_xmm(reg, R(RSCRATCH2));
RI.fregs[reg] = I; RI.fregs[reg] = I;
regNormalRegClear(RI, I);
break; break;
} }
case LoadPaired: case LoadPaired:
@ -1624,8 +1622,6 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, u32 exitAddress)
if (RI.IInfo[I - RI.FirstI] & 4) if (RI.IInfo[I - RI.FirstI] & 4)
fregClearInst(RI, getOp1(I)); fregClearInst(RI, getOp1(I));
if (RI.IInfo[I - RI.FirstI] & 8)
regClearInst(RI, getOp2(I));
break; break;
} }
case StoreDouble: case StoreDouble:
@ -1646,8 +1642,6 @@ static void DoWriteCode(IRBuilder* ibuild, JitIL* Jit, u32 exitAddress)
if (RI.IInfo[I - RI.FirstI] & 4) if (RI.IInfo[I - RI.FirstI] & 4)
fregClearInst(RI, getOp1(I)); fregClearInst(RI, getOp1(I));
if (RI.IInfo[I - RI.FirstI] & 8)
regClearInst(RI, getOp2(I));
break; break;
} }
case StorePaired: case StorePaired: