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Fix twi/tw instructions being switched in Jit64 and JitArm; downgrade the ERROR_LOG printed when tw is ran in the interpreter to DEBUG

This commit is contained in:
Zhuowei Zhang 2014-09-07 13:21:29 -04:00
parent b70c0ae521
commit e63f7c01a3
3 changed files with 6 additions and 6 deletions
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2
Source/Core/Core/PowerPC/Interpreter/Interpreter_Integer.cpp
View File

@ -413,7 +413,7 @@ void Interpreter::tw(UGeckoInstruction _inst)
s32 b = m_GPR[_inst.RB]; s32 b = m_GPR[_inst.RB];
s32 TO = _inst.TO; s32 TO = _inst.TO;
ERROR_LOG(POWERPC, "tw rA %0x rB %0x TO %0x", a, b, TO); DEBUG_LOG(POWERPC, "tw rA %0x rB %0x TO %0x", a, b, TO);
if (((a < b) && (TO & 0x10)) || if (((a < b) && (TO & 0x10)) ||
((a > b) && (TO & 0x08)) || ((a > b) && (TO & 0x08)) ||

4
Source/Core/Core/PowerPC/Jit64/Jit_Integer.cpp
View File

@ -2000,9 +2000,9 @@ void Jit64::twx(UGeckoInstruction inst)
gpr.KillImmediate(a, true, false); gpr.KillImmediate(a, true, false);
if (inst.OPCD == 3) // twi if (inst.OPCD == 3) // twi
CMP(32, gpr.R(a), gpr.R(inst.RB));
else // tw
CMP(32, gpr.R(a), Imm32((s32)(s16)inst.SIMM_16)); CMP(32, gpr.R(a), Imm32((s32)(s16)inst.SIMM_16));
else // tw
CMP(32, gpr.R(a), gpr.R(inst.RB));
std::vector<FixupBranch> fixups; std::vector<FixupBranch> fixups;
CCFlags conditions[] = { CC_A, CC_B, CC_E, CC_G, CC_L }; CCFlags conditions[] = { CC_A, CC_B, CC_E, CC_G, CC_L };

6
Source/Core/Core/PowerPC/JitArm32/JitArm_Integer.cpp
View File

@ -915,12 +915,12 @@ void JitArm::twx(UGeckoInstruction inst)
if (inst.OPCD == 3) // twi if (inst.OPCD == 3) // twi
{ {
CMP(gpr.R(a), gpr.R(inst.RB)); MOVI2R(RB, (s32)(s16)inst.SIMM_16);
CMP(gpr.R(a), RB);
} }
else // tw else // tw
{ {
MOVI2R(RB, (s32)(s16)inst.SIMM_16); CMP(gpr.R(a), gpr.R(inst.RB));
CMP(gpr.R(a), RB);
} }
FixupBranch al = B_CC(CC_LT); FixupBranch al = B_CC(CC_LT);