From e5f2dcd891bc126b5e75e6858ae8040c67df509a Mon Sep 17 00:00:00 2001 From: JosJuice Date: Thu, 13 May 2021 14:10:15 +0200 Subject: [PATCH] JitArm64: Implement FPRF updates for fres+frsqrte --- .../JitArm64/JitArm64_FloatingPoint.cpp | 18 ++++++++++++++---- .../Core/PowerPC/JitArm64/JitArm64_Paired.cpp | 6 ++++-- 2 files changed, 18 insertions(+), 6 deletions(-) diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp index 47cdd42de7..649a70037a 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_FloatingPoint.cpp @@ -24,8 +24,16 @@ void JitArm64::SetFPRFIfNeeded(bool single, ARM64Reg reg) gpr.Lock(ARM64Reg::W0, ARM64Reg::W1, ARM64Reg::W2, ARM64Reg::W3, ARM64Reg::W4, ARM64Reg::W30); - reg = single ? EncodeRegToSingle(reg) : EncodeRegToDouble(reg); - m_float_emit.FMOV(single ? ARM64Reg::W0 : ARM64Reg::X0, reg); + const ARM64Reg routine_input_reg = single ? ARM64Reg::W0 : ARM64Reg::X0; + if (IsVector(reg)) + { + m_float_emit.FMOV(routine_input_reg, single ? EncodeRegToSingle(reg) : EncodeRegToDouble(reg)); + } + else if (reg != routine_input_reg) + { + MOV(routine_input_reg, reg); + } + BL(single ? GetAsmRoutines()->fprf_single : GetAsmRoutines()->fprf_double); gpr.Unlock(ARM64Reg::W0, ARM64Reg::W1, ARM64Reg::W2, ARM64Reg::W3, ARM64Reg::W4, ARM64Reg::W30); @@ -435,7 +443,6 @@ void JitArm64::fresx(UGeckoInstruction inst) INSTRUCTION_START JITDISABLE(bJITFloatingPointOff); FALLBACK_IF(inst.Rc); - FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF); const u32 b = inst.FB; const u32 d = inst.FD; @@ -454,6 +461,8 @@ void JitArm64::fresx(UGeckoInstruction inst) const ARM64Reg VD = fpr.RW(d, RegType::Duplicated); m_float_emit.FMOV(EncodeRegToDouble(VD), ARM64Reg::X0); + + SetFPRFIfNeeded(false, ARM64Reg::X0); } void JitArm64::frsqrtex(UGeckoInstruction inst) @@ -461,7 +470,6 @@ void JitArm64::frsqrtex(UGeckoInstruction inst) INSTRUCTION_START JITDISABLE(bJITFloatingPointOff); FALLBACK_IF(inst.Rc); - FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF); const u32 b = inst.FB; const u32 d = inst.FD; @@ -480,6 +488,8 @@ void JitArm64::frsqrtex(UGeckoInstruction inst) const ARM64Reg VD = fpr.RW(d, RegType::LowerPair); m_float_emit.FMOV(EncodeRegToDouble(VD), ARM64Reg::X0); + + SetFPRFIfNeeded(false, ARM64Reg::X0); } // Since the following float conversion functions are used in non-arithmetic PPC float diff --git a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Paired.cpp b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Paired.cpp index ebbfe3fbd2..1808d14f51 100644 --- a/Source/Core/Core/PowerPC/JitArm64/JitArm64_Paired.cpp +++ b/Source/Core/Core/PowerPC/JitArm64/JitArm64_Paired.cpp @@ -359,7 +359,6 @@ void JitArm64::ps_res(UGeckoInstruction inst) INSTRUCTION_START JITDISABLE(bJITPairedOff); FALLBACK_IF(inst.Rc); - FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF); const u32 b = inst.FB; const u32 d = inst.FD; @@ -383,6 +382,8 @@ void JitArm64::ps_res(UGeckoInstruction inst) fpr.Unlock(ARM64Reg::Q0); fpr.FixSinglePrecision(d); + + SetFPRFIfNeeded(true, VD); } void JitArm64::ps_rsqrte(UGeckoInstruction inst) @@ -390,7 +391,6 @@ void JitArm64::ps_rsqrte(UGeckoInstruction inst) INSTRUCTION_START JITDISABLE(bJITPairedOff); FALLBACK_IF(inst.Rc); - FALLBACK_IF(SConfig::GetInstance().bFPRF && js.op->wantsFPRF); const u32 b = inst.FB; const u32 d = inst.FD; @@ -414,4 +414,6 @@ void JitArm64::ps_rsqrte(UGeckoInstruction inst) fpr.Unlock(ARM64Reg::Q0); fpr.FixSinglePrecision(d); + + SetFPRFIfNeeded(true, VD); }