Core/Common: Add support for low 8 bit parts of SI,DI,BP on 64 bit in x64Emitter
In addition protect against their use on 32 bit and the use of [ABCD]H together with a REX prefix on 64 bit. This assumes that the customOp parameter of WriteREX and operandReg of OpArg always are registers, and thus needs to give something valid to WriteREX when that is not the case (WriteShift). In addition to the patch i sent to the ML, there are a few changes to the error reporting(mostly whitespace). git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@7202 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
pierre
parent
febd967907
commit
e57406dbcc
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@ -133,21 +133,37 @@ void XEmitter::WriteSIB(int scale, int index, int base)
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Write8((u8)((scale << 6) | ((index & 7) << 3) | (base & 7)));
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}
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void OpArg::WriteRex(XEmitter *emit, bool op64, int customOp) const
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void OpArg::WriteRex(XEmitter *emit, int opBits, int bits, int customOp) const
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{
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if (customOp == -1) customOp = operandReg;
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#ifdef _M_X64
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u8 op = 0x40;
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if (customOp == -1) customOp = operandReg;
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if (op64) op |= 8;
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if (customOp >> 3) op |= 4;
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if (indexReg >> 3) op |= 2;
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if (offsetOrBaseReg >> 3) op |= 1; //TODO investigate if this is dangerous
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if (op != 0x40)
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if (opBits == 64) op |= 8;
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if (customOp & 8) op |= 4;
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if (indexReg & 8) op |= 2;
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if (offsetOrBaseReg & 8) op |= 1; //TODO investigate if this is dangerous
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if (op != 0x40 ||
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(bits == 8 && (offsetOrBaseReg & 0x10c) == 4) ||
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(opBits == 8 && (customOp & 0x10c) == 4)) {
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emit->Write8(op);
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_dbg_assert_(DYNA_REC, (offsetOrBaseReg & 0x100) == 0 || bits != 8);
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_dbg_assert_(DYNA_REC, (customOp & 0x100) == 0 || opBits != 8);
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} else {
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_dbg_assert_(DYNA_REC, (offsetOrBaseReg & 0x10c) == 0 ||
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(offsetOrBaseReg & 0x10c) == 0x104 ||
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bits != 8);
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_dbg_assert_(DYNA_REC, (customOp & 0x10c) == 0 ||
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(customOp & 0x10c) == 0x104 ||
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opBits != 8);
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}
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#else
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_dbg_assert_(DYNA_REC, (operandReg >> 3) == 0);
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_dbg_assert_(DYNA_REC, (indexReg >> 3) == 0);
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_dbg_assert_(DYNA_REC, (offsetOrBaseReg >> 3) == 0);
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_dbg_assert_(DYNA_REC, opBits != 64);
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_dbg_assert_(DYNA_REC, (customOp & 8) == 0 || customOp == -1);
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_dbg_assert_(DYNA_REC, (indexReg & 8) == 0);
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_dbg_assert_(DYNA_REC, (offsetOrBaseReg & 8) == 0);
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_dbg_assert_(DYNA_REC, opBits != 8 || (customOp & 0x10c) != 4 || customOp == -1);
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_dbg_assert_(DYNA_REC, bits != 8 || (offsetOrBaseReg & 0x10c) != 4);
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#endif
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}
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@ -169,10 +185,10 @@ void OpArg::WriteRest(XEmitter *emit, int extraBytes, X64Reg _operandReg) const
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#ifdef _M_X64
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u64 ripAddr = (u64)emit->GetCodePtr() + 4 + extraBytes;
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s64 distance = (s64)offset - (s64)ripAddr;
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if (distance >= 0x0000000080000000LL
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|| distance < -0x0000000080000000LL) {
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PanicAlert("WriteRest: op out of range (0x%llx uses 0x%llx)", ripAddr, offset);
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}
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_assert_msg_(DYNA_REC, distance < 0x80000000LL
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&& distance >= -0x80000000LL,
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"WriteRest: op out of range (0x%llx uses 0x%llx)",
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ripAddr, offset);
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s32 offs = (s32)distance;
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emit->Write32((u32)offs);
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#else
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@ -299,17 +315,20 @@ void XEmitter::JMP(const u8 *addr, bool force5Bytes)
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u64 fn = (u64)addr;
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if (!force5Bytes)
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{
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s64 distance = (s64)(fn - ((u64)code + 2)); //TODO - sanity check
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_assert_msg_(DYNA_REC, distance >= -0x80 && distance < 0x80, "Jump target too far away, needs force5Bytes = true");
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s64 distance = (s64)(fn - ((u64)code + 2));
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_assert_msg_(DYNA_REC, distance >= -0x80 && distance < 0x80,
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"Jump target too far away, needs force5Bytes = true");
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//8 bits will do
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Write8(0xEB);
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Write8((u8)(s8)distance);
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}
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else
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{
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s64 distance = (s64)(fn - ((u64)code + 5)); //TODO - sanity check
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s64 distance = (s64)(fn - ((u64)code + 5));
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_assert_msg_(DYNA_REC, distance >= -0x80000000LL && distance < 0x80000000LL, "Jump target too far away, needs indirect register");
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_assert_msg_(DYNA_REC, distance >= -0x80000000LL
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&& distance < 0x80000000LL,
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"Jump target too far away, needs indirect register");
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Write8(0xE9);
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Write32((u32)(s32)distance);
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}
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@ -320,7 +339,7 @@ void XEmitter::JMPptr(const OpArg &arg2)
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OpArg arg = arg2;
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if (arg.IsImm()) _assert_msg_(DYNA_REC, 0, "JMPptr - Imm argument");
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arg.operandReg = 4;
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arg.WriteRex(this, false);
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arg.WriteRex(this, 0, 0);
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Write8(0xFF);
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arg.WriteRest(this);
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}
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@ -337,7 +356,7 @@ void XEmitter::CALLptr(OpArg arg)
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{
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if (arg.IsImm()) _assert_msg_(DYNA_REC, 0, "CALLptr - Imm argument");
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arg.operandReg = 2;
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arg.WriteRex(this, false);
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arg.WriteRex(this, 0, 0);
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Write8(0xFF);
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arg.WriteRest(this);
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}
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@ -345,10 +364,9 @@ void XEmitter::CALLptr(OpArg arg)
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void XEmitter::CALL(const void *fnptr)
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{
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u64 distance = u64(fnptr) - (u64(code) + 5);
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if (distance >= 0x0000000080000000ULL
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&& distance < 0xFFFFFFFF80000000ULL) {
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PanicAlert("CALL out of range (%p calls %p)", code, fnptr);
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}
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_assert_msg_(DYNA_REC, distance < 0x0000000080000000ULL
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|| distance >= 0xFFFFFFFF80000000ULL,
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"CALL out of range (%p calls %p)", code, fnptr);
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Write8(0xE8);
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Write32(u32(distance));
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}
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@ -405,8 +423,10 @@ void XEmitter::J_CC(CCFlags conditionCode, const u8 * addr, bool force5Bytes)
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}
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else
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{
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s64 distance = (s64)(fn - ((u64)code + 6)); //TODO - sanity check
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_assert_msg_(DYNA_REC, distance >= -0x80000000LL && distance < 0x80000000LL, "Jump target too far away, needs indirect register");
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s64 distance = (s64)(fn - ((u64)code + 6));
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_assert_msg_(DYNA_REC, distance >= -0x80000000LL
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&& distance < 0x80000000LL,
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"Jump target too far away, needs indirect register");
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Write8(0x0F);
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Write8(0x80 + conditionCode);
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Write32((u32)(s32)distance);
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@ -438,7 +458,7 @@ void XEmitter::INC(int bits, OpArg arg)
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if (arg.IsImm()) _assert_msg_(DYNA_REC, 0, "INC - Imm argument");
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arg.operandReg = 0;
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if (bits == 16) {Write8(0x66);}
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arg.WriteRex(this, bits == 64);
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arg.WriteRex(this, bits, bits);
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Write8(bits == 8 ? 0xFE : 0xFF);
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arg.WriteRest(this);
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}
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@ -447,7 +467,7 @@ void XEmitter::DEC(int bits, OpArg arg)
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if (arg.IsImm()) _assert_msg_(DYNA_REC, 0, "DEC - Imm argument");
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arg.operandReg = 1;
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if (bits == 16) {Write8(0x66);}
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arg.WriteRex(this, bits == 64);
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arg.WriteRex(this, bits, bits);
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Write8(bits == 8 ? 0xFE : 0xFF);
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arg.WriteRest(this);
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}
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@ -569,7 +589,7 @@ void XEmitter::PUSH(int bits, const OpArg ®)
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{
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if (bits == 16)
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Write8(0x66);
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reg.WriteRex(this, bits == 64);
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reg.WriteRex(this, bits, bits);
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Write8(0xFF);
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reg.WriteRest(this, 0, (X64Reg)6);
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}
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@ -615,7 +635,7 @@ void XEmitter::PREFETCH(PrefetchLevel level, OpArg arg)
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{
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if (arg.IsImm()) _assert_msg_(DYNA_REC, 0, "PREFETCH - Imm argument");;
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arg.operandReg = (u8)level;
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arg.WriteRex(this, false);
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arg.WriteRex(this, 0, 0);
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Write8(0x0F);
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Write8(0x18);
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arg.WriteRest(this);
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@ -625,7 +645,7 @@ void XEmitter::SETcc(CCFlags flag, OpArg dest)
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{
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if (dest.IsImm()) _assert_msg_(DYNA_REC, 0, "SETcc - Imm argument");
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dest.operandReg = 0;
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dest.WriteRex(this, false);
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dest.WriteRex(this, 0, 0);
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Write8(0x0F);
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Write8(0x90 + (u8)flag);
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dest.WriteRest(this);
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@ -635,7 +655,7 @@ void XEmitter::CMOVcc(int bits, X64Reg dest, OpArg src, CCFlags flag)
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{
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if (src.IsImm()) _assert_msg_(DYNA_REC, 0, "CMOVcc - Imm argument");
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src.operandReg = dest;
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src.WriteRex(this, bits == 64);
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src.WriteRex(this, bits, bits);
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Write8(0x0F);
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Write8(0x40 + (u8)flag);
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src.WriteRest(this);
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@ -646,7 +666,7 @@ void XEmitter::WriteMulDivType(int bits, OpArg src, int ext)
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if (src.IsImm()) _assert_msg_(DYNA_REC, 0, "WriteMulDivType - Imm argument");
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src.operandReg = ext;
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if (bits == 16) Write8(0x66);
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src.WriteRex(this, bits == 64);
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src.WriteRex(this, bits, bits);
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if (bits == 8)
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{
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Write8(0xF6);
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@ -670,7 +690,7 @@ void XEmitter::WriteBitSearchType(int bits, X64Reg dest, OpArg src, u8 byte2)
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if (src.IsImm()) _assert_msg_(DYNA_REC, 0, "WriteBitSearchType - Imm argument");
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src.operandReg = (u8)dest;
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if (bits == 16) Write8(0x66);
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src.WriteRex(this, bits == 64);
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src.WriteRex(this, bits, bits);
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Write8(0x0F);
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Write8(byte2);
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src.WriteRest(this);
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@ -694,7 +714,7 @@ void XEmitter::MOVSX(int dbits, int sbits, X64Reg dest, OpArg src)
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}
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src.operandReg = (u8)dest;
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if (dbits == 16) Write8(0x66);
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src.WriteRex(this, dbits == 64);
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src.WriteRex(this, dbits, sbits);
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if (sbits == 8)
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{
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Write8(0x0F);
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@ -725,7 +745,8 @@ void XEmitter::MOVZX(int dbits, int sbits, X64Reg dest, OpArg src)
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}
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src.operandReg = (u8)dest;
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if (dbits == 16) Write8(0x66);
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src.WriteRex(this, dbits == 64);
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//the 32bit result is automatically zero extended to 64bit
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src.WriteRex(this, dbits == 64 ? 32 : dbits, sbits);
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if (sbits == 8)
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{
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Write8(0x0F);
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@ -749,7 +770,7 @@ void XEmitter::LEA(int bits, X64Reg dest, OpArg src)
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if (src.IsImm()) _assert_msg_(DYNA_REC, 0, "LEA - Imm argument");
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src.operandReg = (u8)dest;
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if (bits == 16) Write8(0x66); //TODO: performance warning
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src.WriteRex(this, bits == 64);
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src.WriteRex(this, bits, bits);
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Write8(0x8D);
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src.WriteRest(this);
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}
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@ -768,7 +789,7 @@ void XEmitter::WriteShift(int bits, OpArg dest, OpArg &shift, int ext)
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}
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dest.operandReg = ext;
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if (bits == 16) Write8(0x66);
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dest.WriteRex(this, bits == 64);
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dest.WriteRex(this, bits, bits, 0);
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if (shift.GetImmBits() == 8)
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{
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//ok an imm
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@ -808,7 +829,7 @@ void OpArg::WriteSingleByteOp(XEmitter *emit, u8 op, X64Reg _operandReg, int bit
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emit->Write8(0x66);
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this->operandReg = (u8)_operandReg;
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WriteRex(emit, bits == 64);
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WriteRex(emit, bits, bits);
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emit->Write8(op);
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WriteRest(emit);
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}
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@ -830,7 +851,7 @@ void OpArg::WriteNormalOp(XEmitter *emit, bool toRM, NormalOp op, const OpArg &o
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if (operand.IsImm())
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{
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_operandReg = (X64Reg)0;
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WriteRex(emit, bits == 64);
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WriteRex(emit, bits, bits);
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if (!toRM)
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{
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@ -875,7 +896,7 @@ void OpArg::WriteNormalOp(XEmitter *emit, bool toRM, NormalOp op, const OpArg &o
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else
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{
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_operandReg = (X64Reg)operand.offsetOrBaseReg;
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WriteRex(emit, bits == 64, _operandReg);
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WriteRex(emit, bits, bits, _operandReg);
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// mem/reg or reg/reg op
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if (toRM)
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{
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@ -969,7 +990,7 @@ void XEmitter::IMUL(int bits, X64Reg regOp, OpArg a1, OpArg a2)
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if (bits == 16)
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Write8(0x66);
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a1.WriteRex(this, bits == 64, regOp);
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a1.WriteRex(this, bits, bits, regOp);
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if (a2.GetImmBits() == 8) {
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Write8(0x6B);
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@ -1004,7 +1025,7 @@ void XEmitter::IMUL(int bits, X64Reg regOp, OpArg a)
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if (bits == 16)
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Write8(0x66);
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a.WriteRex(this, bits == 64, regOp);
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a.WriteRex(this, bits, bits, regOp);
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Write8(0x0F);
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Write8(0xAF);
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a.WriteRest(this, 0, regOp);
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@ -1018,7 +1039,7 @@ void XEmitter::WriteSSEOp(int size, u8 sseOp, bool packed, X64Reg regOp, OpArg a
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if (!packed)
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Write8(size == 64 ? 0xF2 : 0xF3);
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arg.operandReg = regOp;
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arg.WriteRex(this, false);
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arg.WriteRex(this, 0, 0);
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Write8(0x0F);
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Write8(sseOp);
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arg.WriteRest(this, extrabytes);
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@ -1033,7 +1054,7 @@ void XEmitter::MOVQ_xmm(X64Reg dest, OpArg arg) {
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// This does not display correctly in MSVC's debugger, it thinks it's a MOVD
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arg.operandReg = dest;
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Write8(0x66);
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arg.WriteRex(this, true);
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arg.WriteRex(this, 64, 0);
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Write8(0x0f);
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Write8(0x6E);
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arg.WriteRest(this, 0);
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@ -1055,13 +1076,13 @@ void XEmitter::MOVQ_xmm(OpArg arg, X64Reg src) {
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// This does not display correctly in MSVC's debugger, it thinks it's a MOVD
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arg.operandReg = src;
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Write8(0x66);
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arg.WriteRex(this, true);
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arg.WriteRex(this, 64, 0);
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Write8(0x0f);
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Write8(0x7E);
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arg.WriteRest(this, 0);
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} else {
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arg.operandReg = src;
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arg.WriteRex(this, false);
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arg.WriteRex(this, 0, 0);
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Write8(0x66);
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Write8(0x0f);
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Write8(0xD6);
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@ -1075,7 +1096,7 @@ void XEmitter::WriteMXCSR(OpArg arg, int ext)
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_assert_msg_(DYNA_REC, 0, "MXCSR - invalid operand");
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arg.operandReg = ext;
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arg.WriteRex(this, false);
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arg.WriteRex(this, 0, 0);
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Write8(0x0F);
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Write8(0xAE);
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arg.WriteRest(this);
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@ -1269,7 +1290,7 @@ void XEmitter::PSHUFB(X64Reg dest, OpArg arg) {
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}
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Write8(0x66);
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arg.operandReg = dest;
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arg.WriteRex(this, false);
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arg.WriteRex(this, 0, 0);
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Write8(0x0f);
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Write8(0x38);
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Write8(0x00);
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@ -37,7 +37,8 @@ enum X64Reg
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R12 = 12,R13 = 13,R14 = 14,R15 = 15,
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AL = 0, BL = 3, CL = 1, DL = 2,
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AH = 4, BH = 7, CH = 5, DH = 6,
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SIL = 6, DIL = 7, BPL = 5, SPL = 4,
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AH = 0x104, BH = 0x107, CH = 0x105, DH = 0x106,
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AX = 0, BX = 3, CX = 1, DX = 2,
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SI = 6, DI = 7, BP = 5, SP = 4,
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@ -113,17 +114,17 @@ struct OpArg
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{
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operandReg = 0;
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scale = (u8)_scale;
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offsetOrBaseReg = (u8)rmReg;
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indexReg = (u8)scaledReg;
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offsetOrBaseReg = (u16)rmReg;
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indexReg = (u16)scaledReg;
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//if scale == 0 never mind offseting
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offset = _offset;
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}
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void WriteRex(XEmitter *emit, bool op64, int customOp = -1) const;
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void WriteRex(XEmitter *emit, int opBits, int bits, int customOp = -1) const;
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void WriteRest(XEmitter *emit, int extraBytes=0, X64Reg operandReg=(X64Reg)0xFF) const;
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void WriteSingleByteOp(XEmitter *emit, u8 op, X64Reg operandReg, int bits);
|
||||
// This one is public - must be written to
|
||||
u64 offset; // use RIP-relative as much as possible - 64-bit immediates are not available.
|
||||
u8 operandReg;
|
||||
u16 operandReg;
|
||||
|
||||
void WriteNormalOp(XEmitter *emit, bool toRM, NormalOp op, const OpArg &operand, int bits) const;
|
||||
bool IsImm() const {return scale == SCALE_IMM8 || scale == SCALE_IMM16 || scale == SCALE_IMM32 || scale == SCALE_IMM64;}
|
||||
|
|
@ -162,8 +163,8 @@ struct OpArg
|
|||
}
|
||||
private:
|
||||
u8 scale;
|
||||
u8 offsetOrBaseReg;
|
||||
u8 indexReg;
|
||||
u16 offsetOrBaseReg;
|
||||
u16 indexReg;
|
||||
};
|
||||
|
||||
inline OpArg M(void *ptr) {return OpArg((u64)ptr, (int)SCALE_RIP);}
|
||||
|
|
|
|||
Loading…
Reference in New Issue