Added separate log for DSP LLE.

git-svn-id: https://dolphin-emu.googlecode.com/svn/trunk@2901 8ced0084-cf51-0410-be5f-012b33b47a6e
This commit is contained in:
XTra.KrazzY 2009-04-06 17:12:05 +00:00
parent 1156a0df9e
commit e3e7c88ff1
15 changed files with 58 additions and 56 deletions

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@ -37,6 +37,7 @@ enum LOG_TYPE {
CONSOLE,
DISCIO,
DSPHLE,
DSPLLE,
DSPINTERFACE,
DVDINTERFACE,
DYNA_REC,

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@ -43,6 +43,7 @@ LogManager::LogManager()\
m_Log[LogTypes::GEKKO] = new LogContainer("GEKKO", "IBM CPU");
m_Log[LogTypes::HLE] = new LogContainer("HLE", "HLE");
m_Log[LogTypes::DSPHLE] = new LogContainer("DSPHLE", "DSP HLE");
m_Log[LogTypes::DSPLLE] = new LogContainer("DSPLLE", "DSP LLE");
m_Log[LogTypes::VIDEO] = new LogContainer("Video", "Video Plugin");
m_Log[LogTypes::AUDIO] = new LogContainer("Audio", "Audio Plugin");
m_Log[LogTypes::DYNA_REC] = new LogContainer("JIT", "Dynamic Recompiler");

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@ -495,7 +495,7 @@ void BPWritten(const Bypass& bp)
case BPMEM_TEV_ALPHA_ENV+32:
break;
default:
WARN_LOG(VIDEO, "Unknown Bypass opcode: address = %08x value = %08x", bp.address, bp.newvalue);
WARN_LOG(VIDEO, "Unknown Bypass opcode: address = 0x%08x value = 0x%08x", bp.address, bp.newvalue);
}
}

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@ -32,7 +32,7 @@ namespace DSPInterpreter {
void unknown(const UDSPInstruction& opc)
{
//_assert_msg_(MASTER_LOG, !g_dsp.exception_in_progress_hack, "assert while exception");
ERROR_LOG(DSPHLE, "LLE: Unrecognized opcode 0x%04x, pc 0x%04x", opc.hex, g_dsp.err_pc);
ERROR_LOG(DSPLLE, "LLE: Unrecognized opcode 0x%04x, pc 0x%04x", opc.hex, g_dsp.err_pc);
}
// test register and updates SR accordingly
@ -118,7 +118,7 @@ void rti(const UDSPInstruction& opc)
if ((opc.hex & 0xf) != 0xf)
{
// FIXME: Implement
ERROR_LOG(DSPHLE, "dsp rti opcode");
ERROR_LOG(DSPLLE, "dsp rti opcode");
}
g_dsp.r[R_SR] = dsp_reg_load_stack(DSP_STACK_D);
@ -358,7 +358,7 @@ void ilrr(const UDSPInstruction& opc)
default:
// FIXME: Implement
ERROR_LOG(DSPHLE, "Unknown ILRR: 0x%04x\n", (opc.hex >> 2) & 0x3);
ERROR_LOG(DSPLLE, "Unknown ILRR: 0x%04x\n", (opc.hex >> 2) & 0x3);
}
}
@ -649,7 +649,7 @@ void andfc(const UDSPInstruction& opc)
if (opc.hex & 0xf)
{
// FIXME: Implement
ERROR_LOG(DSPHLE, "dsp_opc.hex_andfc");
ERROR_LOG(DSPLLE, "dsp_opc.hex_andfc");
}
u8 reg = (opc.hex >> 8) & 0x1;
@ -684,7 +684,7 @@ void andf(const UDSPInstruction& opc)
if (opc.hex & 0xf)
{
// FIXME: Implement
ERROR_LOG(DSPHLE, "dsp andf opcode");
ERROR_LOG(DSPLLE, "dsp andf opcode");
}
reg = 0x1e + ((opc.hex >> 8) & 0x1);
@ -719,7 +719,7 @@ void xori(const UDSPInstruction& opc)
if (opc.hex & 0xf)
{
// FIXME: Implement
ERROR_LOG(DSPHLE, "dsp xori opcode");
ERROR_LOG(DSPLLE, "dsp xori opcode");
}
u8 reg = 0x1e + ((opc.hex >> 8) & 0x1);
@ -739,7 +739,7 @@ void andi(const UDSPInstruction& opc)
if (opc.hex & 0xf)
{
// FIXME: Implement
ERROR_LOG(DSPHLE, "dsp andi opcode");
ERROR_LOG(DSPLLE, "dsp andi opcode");
}
u8 reg = 0x1e + ((opc.hex >> 8) & 0x1);
@ -758,7 +758,7 @@ void ori(const UDSPInstruction& opc)
if (opc.hex & 0xf)
{
// FIXME: Implement
ERROR_LOG(DSPHLE, "dsp ori opcode");
ERROR_LOG(DSPLLE, "dsp ori opcode");
return;
}
@ -1180,33 +1180,33 @@ void srbith(const UDSPInstruction& opc)
// done around loops with lots of multiplications.
case 0xa: // M2
ERROR_LOG(DSPHLE, "M2");
ERROR_LOG(DSPLLE, "M2");
break;
// FIXME: Both of these appear in the beginning of the Wind Waker
case 0xb: // M0
ERROR_LOG(DSPHLE, "M0");
ERROR_LOG(DSPLLE, "M0");
break;
// 15-bit precision? clamping? no idea :(
// CLR15 seems to be the default.
case 0xc: // CLR15
ERROR_LOG(DSPHLE, "CLR15");
ERROR_LOG(DSPLLE, "CLR15");
break;
case 0xd: // SET15
ERROR_LOG(DSPHLE, "SET15");
ERROR_LOG(DSPLLE, "SET15");
break;
// 40-bit precision? clamping? no idea :(
// 40 seems to be the default.
case 0xe: // SET40 (really, clear SR's 0x4000?) something about "set 40-bit operation"?
g_dsp.r[R_SR] &= ~(1 << 14);
ERROR_LOG(DSPHLE, "SET40");
ERROR_LOG(DSPLLE, "SET40");
break;
case 0xf: // SET16 (really, set SR's 0x4000?) something about "set 16-bit operation"?
// that doesnt happen on a real console << what does this comment mean?
g_dsp.r[R_SR] |= (1 << 14);
ERROR_LOG(DSPHLE, "SET16");
ERROR_LOG(DSPLLE, "SET16");
break;
default:

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@ -55,7 +55,7 @@ jnz, ifs, retlnz
#include "DSPJit.h"
#include "gdsp_ext_op.h"
void nop(const UDSPInstruction& opc) {/*DSPInterpreter::unknown(opc);*/}
void nop(const UDSPInstruction& opc) {if(opc.hex) DSPInterpreter::unknown(opc);}
// Unknown Ops
// All AX games: a100
@ -366,7 +366,7 @@ void InitInstructionTable()
}
else
{
ERROR_LOG(DSPHLE, "opcode table place %d already in use for %s", i, opcodes[j].name);
ERROR_LOG(DSPLLE, "opcode table place %d already in use for %s", i, opcodes[j].name);
}
}
}

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@ -29,8 +29,8 @@ extern u32 m_addressPBs;
bool AXTask(u32& _uMail)
{
u32 uAddress = _uMail;
DEBUG_LOG(DSPHLE, "AXTask - ================================================================");
DEBUG_LOG(DSPHLE, "AXTask - AXCommandList-Addr: 0x%08x", uAddress);
DEBUG_LOG(DSPLLE, "AXTask - ================================================================");
DEBUG_LOG(DSPLLE, "AXTask - AXCommandList-Addr: 0x%08x", uAddress);
bool bExecuteList = true;
@ -46,7 +46,7 @@ bool AXTask(u32& _uMail)
case 0: // AXLIST_STUDIOADDR: //00
{
uAddress += 4;
DEBUG_LOG(DSPHLE, "AXLIST AXLIST_SBUFFER: %08x", uAddress);
DEBUG_LOG(DSPLLE, "AXLIST AXLIST_SBUFFER: %08x", uAddress);
}
break;
@ -55,7 +55,7 @@ bool AXTask(u32& _uMail)
{
m_addressPBs = Memory_Read_U32(uAddress);
uAddress += 4;
DEBUG_LOG(DSPHLE, "AXLIST PB address: %08x", m_addressPBs);
DEBUG_LOG(DSPLLE, "AXLIST PB address: %08x", m_addressPBs);
bExecuteList = false;
}
break;
@ -64,7 +64,7 @@ bool AXTask(u32& _uMail)
{
// Hopefully this is where in main ram to write.
uAddress += 4;
DEBUG_LOG(DSPHLE, "AXLIST AXLIST_SBUFFER: %08x", uAddress);
DEBUG_LOG(DSPLLE, "AXLIST AXLIST_SBUFFER: %08x", uAddress);
}
break;
@ -73,15 +73,15 @@ bool AXTask(u32& _uMail)
default:
{
// Stop the execution of this TaskList
DEBUG_LOG(DSPHLE, "AXLIST default: %08x", uAddress);
DEBUG_LOG(DSPLLE, "AXLIST default: %08x", uAddress);
bExecuteList = false;
}
break;
} // end of switch
}
DEBUG_LOG(DSPHLE, "AXTask - done, send resume");
DEBUG_LOG(DSPHLE, "AXTask - ================================================================");
DEBUG_LOG(DSPLLE, "AXTask - done, send resume");
DEBUG_LOG(DSPLLE, "AXTask - ================================================================");
// now resume
return true;

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@ -318,7 +318,7 @@ void Logging()
// Print
INFO_LOG(DSPHLE, "%s", sbuff.c_str());
INFO_LOG(DSPLLE, "%s", sbuff.c_str());
sbuff.clear(); strcpy(buffer, "");
// ---------------
k=0;

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@ -62,7 +62,7 @@ int ReadOutPBs(AXParamBlock * _pPBs, int _num)
// Create a shortcut that let us update struct members
short * pDest = (short *) & _pPBs[i];
if (n > 20 && logall) {DEBUG_LOG(DSPHLE, "%c%i:", 223, i);} // logging
if (n > 20 && logall) {DEBUG_LOG(DSPLLE, "%c%i:", 223, i);} // logging
// Here we update the PB. We do it by going through all 192 / 2 = 96 u16 values
for (size_t p = 0; p < sizeof(AXParamBlock) / 2; p++)
@ -73,7 +73,7 @@ int ReadOutPBs(AXParamBlock * _pPBs, int _num)
{
if (pSrc[p] != 0 && n > 20 && logall)
{
DEBUG_LOG(DSPHLE, "%i %04x | ", p, Common::swap16(pSrc[p]));
DEBUG_LOG(DSPLLE, "%i %04x | ", p, Common::swap16(pSrc[p]));
}
}
@ -81,7 +81,7 @@ int ReadOutPBs(AXParamBlock * _pPBs, int _num)
}
if(n > 20 && logall) {DEBUG_LOG(DSPHLE, "\n");} // logging
if(n > 20 && logall) {DEBUG_LOG(DSPLLE, "\n");} // logging
// Here we update the block address to the starting point of the next PB
blockAddr = (_pPBs[i].next_pb_hi << 16) | _pPBs[i].next_pb_lo;
// save some values

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@ -239,7 +239,7 @@ char* gd_dis_params(gd_globals_t* gdg, const DSPOPCTemplate* opc, u16 op1, u16 o
break;
default:
ERROR_LOG(DSPHLE, "Unknown parameter type: %x", opc->params[j].type);
ERROR_LOG(DSPLLE, "Unknown parameter type: %x", opc->params[j].type);
// exit(-1);
break;
}
@ -288,7 +288,7 @@ u16 gd_dis_get_opcode_size(gd_globals_t* gdg)
if (!opc)
{
ERROR_LOG(DSPHLE, "get_opcode_size ARGH");
ERROR_LOG(DSPLLE, "get_opcode_size ARGH");
exit(0);
}
@ -312,7 +312,7 @@ u16 gd_dis_get_opcode_size(gd_globals_t* gdg)
if (!opc_ext)
{
ERROR_LOG(DSPHLE, "get_opcode_size ext ARGH");
ERROR_LOG(DSPLLE, "get_opcode_size ext ARGH");
}
return opc_ext->size;

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@ -91,7 +91,7 @@ u16 dsp_read_aram()
default:
val = (g_dspInitialize.pARAM_Read_U8(Address) << 8) | g_dspInitialize.pARAM_Read_U8(Address + 1);
Address += 2;
ERROR_LOG(DSPHLE, "Unknown DSP Format %i", gdsp_ifx_regs[DSP_FORMAT]);
ERROR_LOG(DSPLLE, "Unknown DSP Format %i", gdsp_ifx_regs[DSP_FORMAT]);
break;
}

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@ -149,7 +149,7 @@ bool CheckCondition(u8 _Condition)
break;
default:
ERROR_LOG(DSPHLE, "Unknown condition check: 0x%04x\n", _Condition & 0xf);
ERROR_LOG(DSPLLE, "Unknown condition check: 0x%04x\n", _Condition & 0xf);
break;
}

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@ -41,7 +41,7 @@ void dsp_op_ext_r_epi(const UDSPInstruction& opc)
switch (op)
{
case 0x00:
ERROR_LOG(DSPHLE, "dsp_op_ext_r_epi");
ERROR_LOG(DSPLLE, "dsp_op_ext_r_epi");
break;
case 0x01:

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@ -126,7 +126,7 @@ void gdsp_mbox_write_l(u8 mbx, u16 val)
if (mbx == GDSP_MBOX_DSP)
{
DEBUG_LOG(DSPHLE, " - DSP writes mail to mbx %i: 0x%08x (pc=0x%04x)", mbx, gdsp_mbox_peek(GDSP_MBOX_DSP), g_dsp.err_pc);
DEBUG_LOG(DSPLLE, " - DSP writes mail to mbx %i: 0x%08x (pc=0x%04x)", mbx, gdsp_mbox_peek(GDSP_MBOX_DSP), g_dsp.err_pc);
}
}
@ -147,7 +147,7 @@ u16 gdsp_mbox_read_l(u8 mbx)
val = gdsp_mbox[mbx][1];
gdsp_mbox[mbx][0] &= ~0x8000;
DEBUG_LOG(DSPHLE, "- DSP reads mail from mbx %i: %08x (pc=0x%04x)", mbx, gdsp_mbox_peek(mbx), g_dsp.err_pc);
DEBUG_LOG(DSPLLE, "- DSP reads mail from mbx %i: %08x (pc=0x%04x)", mbx, gdsp_mbox_peek(mbx), g_dsp.err_pc);
#if WITH_DSP_ON_THREAD
g_CriticalSection.Leave();
@ -194,9 +194,9 @@ void gdsp_ifx_write(u16 addr, u16 val)
default:
/* if ((addr & 0xff) >= 0xa0 && reg_names[addr - 0xa0])
DEBUG_LOG(DSPHLE, "%04x MW %s (%04x)\n", g_dsp.pc, reg_names[addr - 0xa0], val);
DEBUG_LOG(DSPLLE, "%04x MW %s (%04x)\n", g_dsp.pc, reg_names[addr - 0xa0], val);
else
DEBUG_LOG(DSPHLE, "%04x MW %04x (%04x)\n", g_dsp.pc, addr, val);*/
DEBUG_LOG(DSPLLE, "%04x MW %04x (%04x)\n", g_dsp.pc, addr, val);*/
gdsp_ifx_regs[addr] = val;
break;
}
@ -255,7 +255,7 @@ void gdsp_idma_in(u16 dsp_addr, u32 addr, u32 size)
}
g_dsp.iram_crc = GenerateCRC(g_dsp.cpu_ram + (addr & 0x0fffffff), size);
INFO_LOG(DSPHLE, "*** Copy new UCode from 0x%08x to 0x%04x (crc: %8x)\n", addr, dsp_addr, g_dsp.iram_crc);
INFO_LOG(DSPLLE, "*** Copy new UCode from 0x%08x to 0x%04x (crc: %8x)\n", addr, dsp_addr, g_dsp.iram_crc);
if (g_dsp.dump_imem)
DumpDSPCode(&dst[dsp_addr], size, g_dsp.iram_crc);
@ -264,7 +264,7 @@ void gdsp_idma_in(u16 dsp_addr, u32 addr, u32 size)
void gdsp_idma_out(u16 dsp_addr, u32 addr, u32 size)
{
ERROR_LOG(DSPHLE, "*** idma_out IRAM_DSP (0x%04x) -> RAM (0x%08x) : size (0x%08x)\n", dsp_addr / 2, addr, size);
ERROR_LOG(DSPLLE, "*** idma_out IRAM_DSP (0x%04x) -> RAM (0x%08x) : size (0x%08x)\n", dsp_addr / 2, addr, size);
}
@ -272,7 +272,7 @@ void gdsp_ddma_in(u16 dsp_addr, u32 addr, u32 size)
{
if ((addr & 0x7FFFFFFF) > 0x01FFFFFF)
{
ERROR_LOG(DSPHLE, "*** ddma_in read from invalid addr (0x%08x)\n", addr);
ERROR_LOG(DSPLLE, "*** ddma_in read from invalid addr (0x%08x)\n", addr);
return;
}
@ -283,7 +283,7 @@ void gdsp_ddma_in(u16 dsp_addr, u32 addr, u32 size)
*(u16*)&dst[dsp_addr + i] = *(u16*)&g_dsp.cpu_ram[(addr + i) & 0x7FFFFFFF];
}
INFO_LOG(DSPHLE, "*** ddma_in RAM (0x%08x) -> DRAM_DSP (0x%04x) : size (0x%08x)\n", addr, dsp_addr / 2, size);
INFO_LOG(DSPLLE, "*** ddma_in RAM (0x%08x) -> DRAM_DSP (0x%04x) : size (0x%08x)\n", addr, dsp_addr / 2, size);
}
@ -291,7 +291,7 @@ void gdsp_ddma_out(u16 dsp_addr, u32 addr, u32 size)
{
if ((addr & 0x7FFFFFFF) > 0x01FFFFFF)
{
ERROR_LOG(DSPHLE, "*** gdsp_ddma_out to invalid addr (0x%08x)\n", addr);
ERROR_LOG(DSPLLE, "*** gdsp_ddma_out to invalid addr (0x%08x)\n", addr);
return;
}
@ -302,7 +302,7 @@ void gdsp_ddma_out(u16 dsp_addr, u32 addr, u32 size)
*(u16*)&g_dsp.cpu_ram[(addr + i) & 0x7FFFFFFF] = *(u16*)&src[dsp_addr + i];
}
INFO_LOG(DSPHLE, "*** ddma_out DRAM_DSP (0x%04x) -> RAM (0x%08x) : size (0x%08x)\n", dsp_addr / 2, addr, size);
INFO_LOG(DSPLLE, "*** ddma_out DRAM_DSP (0x%04x) -> RAM (0x%08x) : size (0x%08x)\n", dsp_addr / 2, addr, size);
}
@ -325,7 +325,7 @@ void gdsp_dma()
if ((ctl > 3) || (len > 0x4000))
{
ERROR_LOG(DSPHLE, "DMA ERROR pc: %04x ctl: %04x addr: %08x da: %04x size: %04x\n", g_dsp.pc, ctl, addr, dsp_addr, len);
ERROR_LOG(DSPLLE, "DMA ERROR pc: %04x ctl: %04x addr: %08x da: %04x size: %04x\n", g_dsp.pc, ctl, addr, dsp_addr, len);
exit(0);
}

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@ -59,14 +59,14 @@ u16 dsp_dmem_read(u16 addr)
break;*/
case 0x8: // 8xxx DROM
ERROR_LOG(DSPHLE, "someone reads from ROM");
ERROR_LOG(DSPLLE, "someone reads from ROM");
return dsp_swap16(g_dsp.drom[addr & DSP_DROM_MASK]);
case 0xf: // Fxxx HW regs
return gdsp_ifx_read(addr);
default: // error
ERROR_LOG(DSPHLE, "%04x DSP ERROR: Read from UNKNOWN (%04x) memory", g_dsp.pc, addr);
ERROR_LOG(DSPLLE, "%04x DSP ERROR: Read from UNKNOWN (%04x) memory", g_dsp.pc, addr);
return 0;
}
}
@ -81,11 +81,11 @@ void dsp_dmem_write(u16 addr, u16 val)
break;
case 0x1: // 1xxx COEF
ERROR_LOG(DSPHLE, "someone writes to COEF");
ERROR_LOG(DSPLLE, "someone writes to COEF");
break;
case 0x8: // 8xxx DROM
ERROR_LOG(DSPHLE, "someone writes to DROM");
ERROR_LOG(DSPLLE, "someone writes to DROM");
/* val = dsp_swap16(val);
g_dsp.drom[addr & DSP_DROM_MASK] = val;*/
break;
@ -95,7 +95,7 @@ void dsp_dmem_write(u16 addr, u16 val)
break;
default: // error
ERROR_LOG(DSPHLE, "%04x DSP ERROR: Write to UNKNOWN (%04x) memory", g_dsp.pc, addr);
ERROR_LOG(DSPLLE, "%04x DSP ERROR: Write to UNKNOWN (%04x) memory", g_dsp.pc, addr);
break;
}
}

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@ -300,7 +300,7 @@ void DSP_WriteMailboxHigh(bool _CPUMailbox, u16 _uHighMail)
{
if (gdsp_mbox_peek(GDSP_MBOX_CPU) & 0x80000000)
{
ERROR_LOG(DSPHLE, "Mailbox isnt empty ... strange");
ERROR_LOG(DSPLLE, "Mailbox isnt empty ... strange");
}
#if PROFILE
@ -314,7 +314,7 @@ void DSP_WriteMailboxHigh(bool _CPUMailbox, u16 _uHighMail)
}
else
{
ERROR_LOG(DSPHLE, "CPU cant write to DSP mailbox");
ERROR_LOG(DSPLLE, "CPU cant write to DSP mailbox");
}
}
@ -327,19 +327,19 @@ void DSP_WriteMailboxLow(bool _CPUMailbox, u16 _uLowMail)
u32 uAddress = gdsp_mbox_peek(GDSP_MBOX_CPU);
u16 errpc = g_dsp.err_pc;
DEBUG_LOG(DSPHLE, "CPU writes mail to mbx 0: 0x%08x (pc=0x%04x)\n", uAddress, errpc);
DEBUG_LOG(DSPLLE, "CPU writes mail to mbx 0: 0x%08x (pc=0x%04x)\n", uAddress, errpc);
// I couldn't find any better way to detect the AX mails so this had to
// do. Please feel free to change it.
if ((errpc == 0x0054 || errpc == 0x0055) && m_addressPBs == 0)
{
DEBUG_LOG(DSPHLE, "AXTask ======== 0x%08x (pc=0x%04x)", uAddress, errpc);
DEBUG_LOG(DSPLLE, "AXTask ======== 0x%08x (pc=0x%04x)", uAddress, errpc);
AXTask(uAddress);
}
}
else
{
ERROR_LOG(DSPHLE, "CPU cant write to DSP mailbox");
ERROR_LOG(DSPLLE, "CPU cant write to DSP mailbox");
}
}