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JitArm64: Optimize addi

This commit is contained in:
degasus 2016-02-28 10:42:06 +01:00
parent 4478146c80
commit e2725792d4
1 changed files with 30 additions and 9 deletions
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39
Source/Core/Core/PowerPC/JitArm64/JitArm64_Integer.cpp
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@ -153,31 +153,52 @@ void JitArm64::addix(UGeckoInstruction inst)
JITDISABLE(bJITIntegerOff); JITDISABLE(bJITIntegerOff);
u32 d = inst.RD, a = inst.RA; u32 d = inst.RD, a = inst.RA;
u32 value = (u32)(s32)inst.SIMM_16; u32 imm = (u32)(s32)inst.SIMM_16;
if (inst.OPCD == 15) if (inst.OPCD == 15)
value <<= 16; {
imm <<= 16;
}
u32 imm_neg = 0u - imm;
if (a) if (a)
{ {
if (gpr.IsImm(a)) if (gpr.IsImm(a))
{ {
gpr.SetImmediate(d, gpr.GetImm(a) + value); gpr.SetImmediate(d, gpr.GetImm(a) + imm);
} }
else else
{ {
gpr.BindToRegister(d, d == a); gpr.BindToRegister(d, d == a);
ARM64Reg WA = gpr.GetReg(); if (imm < 4096)
MOVI2R(WA, value); {
ADD(gpr.R(d), gpr.R(a), WA); ADD(gpr.R(d), gpr.R(a), imm);
gpr.Unlock(WA); }
else if (imm % 4096 == 0 && imm < 4096 * 4096)
{
ADD(gpr.R(d), gpr.R(a), imm / 4096, true);
}
else if (imm_neg < 4096)
{
SUB(gpr.R(d), gpr.R(a), imm_neg);
}
else if (imm_neg % 4096 == 0 && imm_neg < 4096 * 4096)
{
SUB(gpr.R(d), gpr.R(a), imm_neg / 4096, true);
}
else
{
ARM64Reg WA = gpr.GetReg();
MOVI2R(WA, imm);
ADD(gpr.R(d), gpr.R(a), WA);
gpr.Unlock(WA);
}
} }
} }
else else
{ {
// a == 0, implies zero register // a == 0, implies zero register
gpr.SetImmediate(d, value); gpr.SetImmediate(d, imm);
} }
} }